Related papers: Below 100 ps CTR using FastIC+, an ASIC including …

The paper presents a system for measuring photon statistics and photon timing in the few-photon regime down to the single-photon level. The measurement system is based on superconducting nanowire single photon detectors and a…

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM…

The Cherenkov Imaging Telescope Integrated Read Out Chip (CITIROC) is a 32-channel fully analogue front-end ASIC dedicated to the read-out of silicon photo-multiplier (SiPM) sensors that can be used in a variety of experiments with…

We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space…

A new TDC-chip is under development for the COMPASS experiment at CERN. The ASIC, which exploits the 0.6 micrometer CMOS sea-of-gate technology, will allow high resolution time measurements with digitization of 75 ps, and an unprecedented…

1 ps timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe a preliminary design for PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in the TSMC 65…

In the last years, high-resolution time tagging has emerged as the tool to tackle the problem of high-track density in the detectors of the next generation of experiments at particle colliders. Time resolutions below 50ps and event average…

The MIP Timing Detector will provide additional timing capabilities for detection of minimum ionizing particles (MIPs) at CMS during the High Luminosity LHC era, improving event reconstruction and pileup rejection. The central portion of…

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC)…

Timepix3 is a multi-purpose readout ASIC for hybrid pixel detectors. It can measure time and energy simultaneously by employing time-of-arrival (ToA) and time-over-threshold (ToT) techniques. Both methods are systematically affected by…

The prototype of time digitizing system for the upgrade of BESIII endcap TOF (ETOF) is introduced in this paper. The ETOF readout electronics has a formation of distributed architecture that hit signal from multi-gap resistive plate chamber…

The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey…

The design and evaluation on the NSLS-II beamline of the 3FI application specific integrated circuit (ASIC) bump-bonded to a simply, planar, two-dimensionally segmented silicon sensor is presented. The ASIC was developed for Full-Field…

The aim of this work is to develop high precision Time-of-Flight (TOF) devices based on high refractive index solid Cherenkov radiators read out by silicon photomultipliers (SiPMs). Cherenkov light is prompt and therefore ideal for reaching…

The Multi-Pixel Photon Counter (MPPC) or Silicon Photomultiplier (SiPM) can detect from a single photon to several thousand ones; it has high gain -$10^{5}$ to $10^{6}$-, low operation voltage -65 to 75 Vdc-, and small size -typically 3.85…

We have designed three ASICs for possible applications in the optical links of a new layer of pixel detector in the ATLAS experiment for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL, a…

The design of a detector system comprised of four silicon sensors bump-bonded to Timepix4 ASICs is described together with its data acquisition system, operational infrastructure, and dedicated software. The spatial and temporal performance…

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope…

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream…

The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 {\mu}m CMOS prototype device contains two channels and each channel employs a…