Related papers: Engineering Cryogenic FETs: Addressing SCEs and Im…
In this paper, through careful calibration, we demonstrate the possibility of using a single set of models and parameters to model the ON current and Sub-threshold Slope (SS) of an nMOSFET at 300K and 5K using Technology Computer-Aided…
In this paper, an analytical predictive model of interface charge traps in symmetric long channel double-gate junctionless transistors is proposed based on a charge-based model. Interface charge traps arising from the exposure to chemicals,…
The advancement of quantum technology networks necessitates high-speed, low-thermal load, and minimal-noise communication links between cryogenic and room-temperature components. At the heart of modern telecommunication, lay optical…
This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300, 77 and 4.2…
Cryogenic field-effect transistors (FETs) offer great potential for a wide range of applications, the most notable example being classical control electronics for quantum information processors. In the latter context, on-chip FETs with low…
In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by…
The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold…
Dense arrays of trapped ions provide one way of scaling up ion trap quantum information processing. However, miniaturization of ion traps is currently limited by sharply increasing motional state decoherence at sub-100 um ion-electrode…
Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…
High 1/f noise in CryoCMOS devices is a critical parameter to keep under control in the design of complex circuits for low temperatures applications. Current models predict the 1/f noise to scale linearly with temperature, and gate oxide…
This paper presents an extensive characterization and modeling of a commercial 28-nm FDSOI CMOS process operating down to cryogenic temperatures. The important cryogenic phenomena influencing this technology are discussed. The…
Silicon carbide is a wide-bandgap semiconductor with an emerging CMOS technology platform and it is widely deployed in high power and harsh environment electronics. This material is also attracting interest for quantum technologies through…
Electrical conductivity with gate-sweep in a few layer MoS$_2$-on-SiO$_2$ field-effect-transistor shows an abrupt reduction in hysteresis when cooled. The hysteresis and time dependent conductivity of the MoS$_2$ channel are modeled using…
This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes.…
In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the…
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias…
This study employs advanced phase-field modeling to investigate Si-based qubit MOSFETs, integrating electrostatics and quantum mechanical effects. We adopt a comprehensive modeling approach, utilizing full-wave treatment of the Schrodinger…
Results of detailed simulations of the charge transfer inefficiency of a prototype serial readout CCD chip are reported. The effect of radiation damage on the chip operating in a particle detector at high frequency at a future accelerator…
Current control techniques for cryogenically cooled qubits are realized with coaxial cables, posing multiple challenges in terms of cost, thermal load, size, and long-term scalability. Emerging approaches to tackle this issue include…
This work presents a self-heating study of a 40-nm bulk-CMOS technology in the ambient temperature range from 300 K down to 4.2 K. A custom test chip was designed and fabricated for measuring both the temperature rise in the MOSFET channel…