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Manycore processors feature a high number of general-purpose cores designed to work in a multithreaded fashion. Recent manycore processors are kept coherent using scalable distributed directories. A paramount example is the Intel Mesh…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-11-12 Steve Kommrusch , Marcos Horro , Louis-Noël Pouchet , Gabriel Rodríguez , Juan Touriño

The network topology and the routing strategy are major factors to affect the traffic dynamics of the network. In this work, we aim to design an optimal time-varying network structure and an efficient route is allocated to each user in the…

Networking and Internet Architecture · Computer Science 2019-09-18 Suchi Kumari , Anurag Singh

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those…

Hardware Architecture · Computer Science 2022-11-07 Simran Preet Kaur , Manojit Ghose , Ananya Pathak , Rutuja Patole

Integrated optical interconnect is believed to be one of the main technologies to replace electrical wires. Optical Network-on-Chip (ONoC) has attracted more attentions nowadays. Benes topology is a good choice for ONoC for its…

Hardware Architecture · Computer Science 2011-09-06 Jing Zhang , Huaxi Gu , Yintang Yang

Networks-on-Chip (NoCs) for future many-core processor platforms integrate more and more heterogeneous components of different types and many real-time and latency-sensitive applications can run on a single chip concurrently. The…

Hardware Architecture · Computer Science 2011-09-06 Peibo Xie , Huaxi Gu

The increasing density of transistors in Integrated Circuits (ICs) has enabled the development of highly integrated Systems-on-Chip (SoCs) and, more recently, Multiprocessor Systems-on-Chip (MPSoCs). To address scalability challenges in…

Hardware Architecture · Computer Science 2025-04-29 Rodrigo Cataldo , Cesar Marcon , Debora Matos

Performance evaluation of the routing node in terms of latency is the characteristics of an efficient design of Buffer in input module. It is intended to study and quantify the behavior of the single packet array design in relation to the…

Hardware Architecture · Computer Science 2013-02-19 Nilesh A. Mohota , Sanjay L. Badjate

In this letter, we propose a new routing strategy to improve the transportation efficiency on complex networks. Instead of using the routing strategy for shortest path, we give a generalized routing algorithm to find the so-called {\it…

Disordered Systems and Neural Networks · Physics 2007-05-23 Gang Yan , Tao Zhou , Bo Hu , Zhong-Qian Fu , Bing-Hong Wang

Efficient deployment of neural networks on resource-constrained hardware demands optimal use of on-chip memory. In event-based processors, this is particularly critical for routing architectures, where substantial memory is dedicated to…

Emerging Technologies · Computer Science 2024-12-03 Jimmy Weber , Theo Ballet , Melika Payvand

Content-Centric Networking (CCN) research addresses the mismatch between the modern usage of the Internet and its outdated architecture. Importantly, CCN routers may locally cache frequently requested content in order to speed up delivery…

Artificial Intelligence · Computer Science 2016-10-14 Harald Beck , Bruno Bierbaumer , Minh Dao-Tran , Thomas Eiter , Hermann Hellwagner , Konstantin Schekotihin

Contrary to orthogonal multiple-access (OMA), non-orthogonal multiple-access (NOMA) schemes can serve a pool of users without exploiting the scarce frequency or time domain resources. This is useful in meeting the sixth generation (6G)…

Information Theory · Computer Science 2023-07-11 Dipen Bepari , Soumen Mondal , Aniruddha Chandra , Rajeev Shukla , Yuanwei Liu , Mohsen Guizani , Arumugam Nallanathan

In networks-on-chip, static routing schemes are favored for their simplicity and predictability, but they cannot effectively balance network load due to the unawareness of runtime load distribution. Q-StaR discovers two factors (topology…

Networking and Internet Architecture · Computer Science 2026-03-12 Yang Zhang , Yiren Zhao , Xu Wang , Fengyuan Ren

Caching networks are designed to reduce traffic load at backhaul links, by serving demands from edge-nodes. In the past decades, many studies have been done to address the caching problem. However, in practice, finding an optimal caching…

Networking and Internet Architecture · Computer Science 2018-07-03 Elahe Rezaei , Hafez Eslami Manoochehri , Babak Hossein Khalaj

RRAM-based multi-core systems improve the energy efficiency and performance of CNNs. Thereby, the distributed parallel execution of convolutional layers causes critical data dependencies that limit the potential speedup. This paper presents…

Hardware Architecture · Computer Science 2023-10-27 Rebecca Pelke , Nils Bosbach , Jose Cubero , Felix Staudigl , Rainer Leupers , Jan Moritz Joseph

We present the design and evaluation of a predictable Network-on-Chip (NoC) to interconnect processing units running multimedia applications with variable-bit-rate. The design is based on a connectionless strategy in which flits from…

Hardware Architecture · Computer Science 2014-11-14 Marcelo Daniel Berejuck , Antônio Augusto Fröhlich

In this paper, we propose a cache-aided non-orthogonal multiple access (NOMA) scheme for spectrally efficient downlink transmission. The proposed scheme not only reaps the benefits associated with NOMA and caching, but also exploits the…

Information Theory · Computer Science 2019-06-26 Lin Xiang , Derrick Wing Kwan Ng , Xiaohu Ge , Zhiguo Ding , Vincent W. S. Wong , Robert Schober

Recent studies in different fields of science caused emergence of needs for high performance computing systems like Cloud. A critical issue in design and implementation of such systems is resource allocation which is directly affected by…

Distributed, Parallel, and Cluster Computing · Computer Science 2016-05-05 Masoud Nosrati , Abdolah Chalechale , Ronak Karimi

The increasing popularity of deep neural network (DNN) applications demands high computing power and efficient hardware accelerator architecture. DNN accelerators use a large number of processing elements (PEs) and on-chip memory for…

Machine Learning · Computer Science 2022-04-28 Binayak Tiwari , Mei Yang , Xiaohang Wang , Yingtao Jiang

Content caching at intermediate nodes is a very effective way to optimize the operations of Computer networks, so that future requests can be served without going back to the origin of the content. Several caching techniques have been…

Networking and Internet Architecture · Computer Science 2014-08-27 Ammar Gharaibeh , Abdallah Khreishah , Issa Khalil , Jie Wu

This paper studies a problem of jointly optimizing two important operations in mobile edge computing without knowing future requests, namely service caching, which determines which services to be hosted at the edge, and service routing,…

Networking and Internet Architecture · Computer Science 2022-02-01 Siqi Fan , I-Hong Hou , Van Sy Mai , Lotfi Benmohamed