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Related papers: Efficient Calibration for RRAM-based In-Memory Com…

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Passive resistive random access memory (ReRAM) crossbar arrays, a promising emerging technology used for analog matrix-vector multiplications, are far superior to their active (1T1R) counterparts in terms of the integration density.…

With the proliferation of mobile devices, the need for an efficient model to restore any degraded image has become increasingly significant and impactful. Traditional approaches typically involve training dedicated models for each specific…

Computer Vision and Pattern Recognition · Computer Science 2024-12-19 Bin Ren , Eduard Zamfir , Zongwei Wu , Yawei Li , Yidi Li , Danda Pani Paudel , Radu Timofte , Ming-Hsuan Yang , Nicu Sebe

Hardware neural networks that implement synaptic weights with embedded non-volatile memory, such as spin torque memory (ST-MRAM), are a major lead for low energy artificial intelligence. In this work, we propose an approximate storage…

Emerging Technologies · Computer Science 2018-10-26 Nicolas Locatelli , Adrien F. Vincent , Damien Querlioz

With the escalating demand for power-efficient neural network architectures, non-volatile compute-in-memory designs have garnered significant attention. However, owing to the nature of analog computation, susceptibility to noise remains a…

Emerging Technologies · Computer Science 2025-02-11 Ying-Hao Wei , Zishen Wan , Brian Crafton , Samuel Spetalnick , Arijit Raychowdhury

A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel…

Hardware Architecture · Computer Science 2021-07-07 Zhiyu Chen , Zhanghao Yu , Qing Jin , Yan He , Jingyu Wang , Sheng Lin , Dai Li , Yanzhi Wang , Kaiyuan Yang

Despite the impressive search rate of one key per clock cycle, the update stage of a random-access-memory-based content-addressable-memory (RAM-based CAM) always suffers high latency. Two primary causes of such latency include: (1) the…

Hardware Architecture · Computer Science 2018-06-28 Xuan-Thuan Nguyen , Trong-Thuc Hoang , Hong-Thu Nguyen , Katsumi Inoue , Cong-Kha Pham

As supercomputers advance towards exascale capabilities, computational intensity increases significantly, and the volume of data requiring storage and transmission experiences exponential growth. Adaptive Mesh Refinement (AMR) has emerged…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-07-20 Daoce Wang , Jesus Pulido , Pascal Grosset , Jiannan Tian , Sian Jin , Houjun Tang , Jean Sexton , Sheng Di , Zarija Lukić , Kai Zhao , Bo Fang , Franck Cappello , James Ahrens , Dingwen Tao

The second-order training methods can converge much faster than first-order optimizers in DNN training. This is because the second-order training utilizes the inversion of the second-order information (SOI) matrix to find a more accurate…

Hardware Architecture · Computer Science 2022-10-28 Yilong Zhao , Li Jiang , Mingyu Gao , Naifeng Jing , Chengyang Gu , Qidong Tang , Fangxin Liu , Tao Yang , Xiaoyao Liang

Resistive Random Access Memory (RRAM) is an emerging device for processing-in-memory (PIM) architecture to accelerate convolutional neural network (CNN). However, due to the highly coupled crossbar structure in the RRAM array, it is…

Hardware Architecture · Computer Science 2020-10-14 Songming Yu , Yongpan Liu , Lu Zhang , Jingyu Wang , Jinshan Yue , Zhuqing Yuan , Xueqing Li , Huazhong Yang

As the demand for efficient, low-power computing in embedded and edge devices grows, traditional computing methods are becoming less effective for handling complex tasks. Stochastic computing (SC) offers a promising alternative by…

Compute-in-memory (CiM) is a promising approach to improving the computing speed and energy efficiency in dataintensive applications. Beyond existing CiM techniques of bitwise logic-in-memory operations and dot product operations, this…

Hardware Architecture · Computer Science 2023-01-03 Yiming Chen , Yushen Fu , Mingyen Lee , Sumitha George , Yongpan Liu , Vijaykrishnan Narayanan , Huazhong Yang , Xueqing Li

Scaling to larger systems, with current levels of reliability, requires cost-effective methods to mitigate hardware failures. One of the main causes of hardware failure is an uncorrected error in memory, which terminates the current job and…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-09-06 Isaac Boixaderas , Sergi Moré , Javier Bartolome , David Vicente , Petar Radojković , Paul M. Carpenter , Eduard Ayguadé

While general-purpose computing follows Von Neumann's architecture, the data movement between memory and processor elements dictates the processor's performance. The evolving compute-in-memory (CiM) paradigm tackles this issue by…

Hardware Architecture · Computer Science 2024-11-15 Dhandeep Challagundla , Ignatius Bezzam , Riadul Islam

Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has found wide-spread adoption in accelerating neural networks for…

Hardware Architecture · Computer Science 2020-08-18 Brian Crafton , Samuel Spetalnick , Gauthaman Murali , Tushar Krishna , Sung-Kyu Lim , Arijit Raychowdhury

This paper presents MEMROC (Multi-Eye to Mobile RObot Calibration), a novel motion-based calibration method that simplifies the process of accurately calibrating multiple cameras relative to a mobile robot's reference frame. MEMROC utilizes…

Robotics · Computer Science 2024-10-14 Davide Allegro , Matteo Terreran , Stefano Ghidoni

MRI is an inherently slow process, which leads to long scan time for high-resolution imaging. The speed of acquisition can be increased by ignoring parts of the data (undersampling). Consequently, this leads to the degradation of image…

Image and Video Processing · Electrical Eng. & Systems 2022-02-22 Soumick Chatterjee , Mario Breitkopf , Chompunuch Sarasaen , Hadya Yassin , Georg Rose , Andreas Nürnberger , Oliver Speck

Obtainable computational efficiency is evaluated when using an Adaptive Mesh Refinement (AMR) strategy in time accurate simulations governed by sets of conservation laws. For a variety of 1D, 2D, and 3D hydro- and magnetohydrodynamic…

Astrophysics · Physics 2009-11-10 R. Keppens , M. Nool , G. Toth , J. P. Goedbloed

The primary operation in DNNs is the dot product of quantized input activations and weights. Prior works have proposed the design of memory-centric architectures based on the Processing-In-Memory (PIM) paradigm. Resistive RAM (ReRAM)…

Hardware Architecture · Computer Science 2023-06-29 Mohammad Sabri , Marc Riera , Antonio González

Computing-in-Memory (CIM) accelerators are a promising solution for accelerating Machine Learning (ML) workloads, as they perform Matrix-Vector Multiplications (MVMs) on crossbar arrays directly in memory. Although the bit widths of the…

Machine Learning · Computer Science 2026-03-20 Rebecca Pelke , Joel Klein , Jose Cubero-Cascante , Nils Bosbach , Jan Moritz Joseph , Rainer Leupers

Fine-tuning helps large language models (LLM) recover degraded information and enhance task performance. Although Low-Rank Adaptation (LoRA) is widely used and effective for fine-tuning, we have observed that its scaling factor can limit or…

Machine Learning · Computer Science 2025-01-14 Jun Liu , Zhenglun Kong , Peiyan Dong , Changdi Yang , Xuan Shen , Pu Zhao , Hao Tang , Geng Yuan , Wei Niu , Wenbin Zhang , Xue Lin , Dong Huang , Yanzhi Wang
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