Related papers: Scalable Superconducting Nanowire Memory Array wit…

This paper summarizes our work on experimentally characterizing, mitigating, and recovering data retention errors in multi-level cell (MLC) NAND flash memory, which was published in HPCA 2015, and examines the work's significance and future…

Computational hardware designed to mimic biological neural networks holds the promise to resolve the drastically growing global energy demand of artificial intelligence. A wide variety of hardware concepts have been proposed, and among…

Of the many potential hardware platforms, superconducting quantum circuits have become the leading contender for constructing a scalable quantum computing system. All current architecture designs necessitate a 2D arrangement of…

This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep Neural Networks. Techniques to do in-situ arithmetic in…

In recent times, the production of multidimensional data in various domains and their storage in array databases has witnessed a sharp increase; this rapid growth in data volumes necessitates compression in array databases. However,…

Superconducting 3D microwave cavities offer state-of-the-art coherence times and a well controlled environment for superconducting qubits. In order to realize at the same time fast readout and long-lived quantum information storage, one can…

This paper describes a new memristor crossbar architecture that is proposed for use in a high density cache design. This design has less than 10% of the write energy consumption than a simple memristor crossbar. Also, it has up to 4 times…

Deep networks are now able to achieve human-level performance on a broad spectrum of recognition tasks. Independently, neuromorphic computing has now demonstrated unprecedented energy-efficiency through a new chip architecture based on…

Scalable, high speed data transfer between cryogenic (0.1-4 K) and room temperature environments is instrumental in a broad range of fields including quantum computing, superconducting electronics, single photon imaging and space-based…

Training convolutional neural networks (CNNs) requires intense computations and high memory bandwidth. We find that bandwidth today is over-provisioned because most memory accesses in CNN training can be eliminated by rearranging…

Multilayered artificial neural networks (ANN) have found widespread utility in classification and recognition applications. The scale and complexity of such networks together with the inadequacies of general purpose computing platforms have…

This work presents E-ReCON, a 16 Kb energy and resource-efficient digital compute-in-memory (DCIM) macro based on a compact 3T1R ReRAM bitcell for edge-AI inference. The proposed bitcell occupies only 0.85 um^2 and supports reliable…

Neuromorphic computing using spin waves is promising for high-speed nanoscale devices, but the realization of high performance has not yet been achieved. Here we show, using micromagnetic simulations and simplified theory with response…

Sparse deep learning has reduced computation significantly, but its irregular non-zero data distribution complicates the data flow and hinders data reuse, increasing on-chip SRAM access and thus power consumption of the chip. This paper…

Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths,…

The nanoPU is a new networking-optimized CPU designed to minimize tail latency for RPCs. By bypassing the cache and memory hierarchy, the nanoPU directly places arriving messages into the CPU register file. The wire-to-wire latency through…

As machine learning applications continue to evolve, the demand for efficient hardware accelerators, specifically tailored for deep neural networks (DNNs), becomes increasingly vital. In this paper, we propose a configurable memory…

We present a 1024-element imaging array of superconducting nanowire single photon detectors (SNSPDs) using a 32x32 row-column multiplexing architecture. Large arrays are desirable for applications such as imaging, spectroscopy, or particle…

In this paper, we present a new 9T SRAM cell that has good write-ability and improves read stability at the same time. Simulation results show that the proposed design increases Read SNM (RSNM) and Ion/Ioff of read path by 219% and 113%,…

Spiking neural networks (SNNs) are being explored in an attempt to mimic brain's capability to learn and recognize at low power. Crossbar architecture with highly scalable Resistive RAM or RRAM array serving as synaptic weights and neuronal…