Related papers: The rIC3 Hardware Model Checker
We present an alternative approach to solve the hardware (HW) and software (SW) partitioning problem, which uses Bounded Model Checking (BMC) based on Satisfiability Modulo Theories (SMT) in conjunction with a multi-core support using Open…
Program analysis is on the brink of mainstream in embedded systems development. Formal verification of behavioural requirements, finding runtime errors and automated test case generation are some of the most common applications of automated…
The ALICE collaboration is preparing an upgrade of the three innermost layers of the current Inner Tracking System (ITS) during the next LHC long shutdown (LS3). The new ITS detector will use wafer-scale (up to \SI{27}{cm} in length)…
Processor design and verification require a synergistic approach that combines instruction-level functional simulations with precise hardware emulations. The trade-off between speed and accuracy in the instruction set simulation poses a…
Algorithm parameters, in particular hyperparameters of machine learning algorithms, can substantially impact their performance. To support users in determining well-performing hyperparameter configurations for their algorithms, datasets and…
During the Long Shutdown 3 (LS3, scheduled 2026-2030), the innermost 3 layers (Inner Barrel, or IB) of the present ALICE ITS2 will be replaced with large-area, flexible, stitched CMOS 65 nm sensors, arranged in 2 half-barrels of 3…
The "LiC Detector Toy" is a fast single-track simulation and reconstruction tool, aiming at the optimization of tracking detector design, i.e. geometric layout and material budgets. Its implementation is based on the MATLAB system.…
Proof-carrying hardware (PCH) is an approach to achieving safety of dynamically reconfigurable hardware, transferring the idea of proof-carrying code to the hardware domain. Current PCH approaches are, however, either limited to…
We introduce a new methodology based on refinement for testing the functional correctness of hardware and low-level software. Our methodology overcomes several major drawbacks of the de facto testing methodologies used in industry: (1) it…
During LHC Long Shutdown 3, the ALICE experiment will replace the three innermost layers of its Inner Tracking System (ITS2) with a new vertex detector, the ITS3. This new detector will be assembled using wafer-scale, stitched Monolithic…
Test optimization contains test case selection and minimization, which is an important challenge in software testing and has been addressed with search-based approaches intensively in the past. Inspired by the recent advancement of using…
Memory consistency models (MCMs) which govern inter-module interactions in a shared memory system, are a significant, yet often under-appreciated, aspect of system design. MCMs are defined at the various layers of the hardware-software…
The ALICE ITS3 is a novel vertex detector replacing the innermost layers of ITS2 during LS3. Composed of three truly cylindrical layers of wafer-sized 65 nm stitched Monolithic Active Pixel Sensors, ITS3 provides high-resolution tracking of…
Model checking is an automatic formal verification technique that is widely used in hardware verification. The state-of-the-art complete model-checking techniques, based on IC3/PDR and its general variant CAR, are based on computing…
In this paper, we tackle the problem of incrementally learning a classifier, one example at a time, directly on chip. To this end, we propose an efficient hardware implementation of a recently introduced incremental learning procedure that…
Modern Systems-on-Chip (SoCs) incorporate built-in self-test (BIST) modules deeply integrated into the device's intellectual property (IP) blocks. Such modules handle hardware faults and defects during device operation. As such, BIST…
This paper presents a novel method to enhance the reliability of image classification models during deployment in the face of transient hardware errors. By utilizing enriched text embeddings derived from GPT-3 with question prompts per…
We present INTELLECT-3, a 106B-parameter Mixture-of-Experts model (12B active) trained with large-scale reinforcement learning on our end-to-end RL infrastructure stack. INTELLECT-3 achieves state of the art performance for its size across…
This paper further extends RIn-Close_CVC, a biclustering algorithm capable of performing an efficient, complete, correct and non-redundant enumeration of maximal biclusters with constant values on columns in numerical datasets. By avoiding…
The importance of preventing microarchitectural timing side channels in security-critical applications has surged in recent years. Constant-time programming has emerged as a best-practice technique for preventing the leakage of secret…