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Modern DRAM modules are often equipped with hardware error correction capabilities, especially for DRAM deployed in large-scale data centers, as process technology scaling has increased the susceptibility of these devices to errors. To…
We propose an Iterative Detection and Decoding (IDD) scheme with Low Density Parity Check (LDPC) codes for Multiple Input Multiple Output (MIMO) systems for block-fading $F = 2$ and fast fading Rayleigh channels. An IDD receiver with soft…
Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the…
We study a problem of constructing codes that transform a channel with high bit error rate (BER) into one with low BER (at the expense of rate). Our focus is on obtaining codes with smooth ("graceful") input-output BER curves (as opposed to…
Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing…
We introduce a two-stage decimation process to improve the performance of neural belief propagation (NBP), recently introduced by Nachmani et al., for short low-density parity-check (LDPC) codes. In the first stage, we build a list by…
Quantum computers hold the potential to surpass classical computers in solving complex computational problems. However, the fragility of quantum information and the error-prone nature of quantum operations make building large-scale,…
Processing-in-Memory (PIM) enhances memory with computational capabilities, potentially solving energy and latency issues associated with data transfer between memory and processors. However, managing concurrent computation and data flow…
This work shows how non-binary low-density parity-check codes over GF($2^p$) can be combined with probabilistic amplitude shaping (PAS) (B\"ocherer, et al., 2015), which combines forward-error correction with non-uniform signaling for…
We analyze the asymptotic performance of nonbinary spatially-coupled low-density parity-check (SC-LDPC) codes built on the general linear group, when the transmission takes place over the binary erasure channel. We propose an efficient…
The huge amount of data produced in the fifth-generation (5G) networks not only brings new challenges to the reliability and efficiency of mobile devices but also drives rapid development of new storage techniques. With the benefits of fast…
Improvements in main memory storage density are primarily driven by process technology scaling, which negatively impacts reliability by exacerbating various circuit-level error mechanisms. To compensate for growing error rates, both memory…
Developing kernels for Processing-In-Memory (PIM) platforms poses unique challenges in data management and parallel programming on limited processing units. Although software development kits (SDKs) for PIM, such as the UPMEM SDK, provide…
The linear error-correcting codes are known to be well suited for battling and correcting the burst errors caused by noise in the wireless data transmission system. However, different types of codes offer different decoding and…
Quantum error-correcting codes protect fragile quantum information by encoding it redundantly, but identifying codes that perform well in practice with minimal overhead remains difficult due to the combinatorial search space and the high…
Departing from traditional communication theory where decoding algorithms are assumed to perform without error, a system where noise perturbs both computational devices and communication channels is considered here. This paper studies…
Processing-in-Memory (PIM) architectures enable computation directly within DRAM and help combat the memory wall problem. Bit-shifting is a fundamental operation that enables PIM applications such as shift-and-add multiplication, adders…
Forward error correcting (FEC) codes are used in many communication standards with a wide range of re quirements. FEC codes should work close to capacity, achieve low error floors, and have low decoding complexity. In this paper, we propose…
Multiple reads of the same Flash memory cell with distinct word-line voltages provide enhanced precision for LDPC decoding. In this paper, the word-line voltages are optimized by maximizing the mutual information (MI) of the quantized…
Linear Programming (LP) decoding of Low-Density Parity-Check (LDPC) codes has attracted much attention in the research community in the past few years. LP decoding has been derived for binary and nonbinary linear codes. However, the most…