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We propose a distributed system based on lowpower embedded FPGAs designed for edge computing applications focused on exploring distributing scheduling optimizations for Deep Learning (DL) workloads to obtain the best performance regarding…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-05-31 Hans Johnson , Tianyang Fang , Alejandro Perez-Vicente , Jafar Saniie

3D reconstruction from videos has become increasingly popular for various applications, including navigation for autonomous driving of robots and drones, augmented reality (AR), and 3D modeling. This task often combines traditional…

Hardware Architecture · Computer Science 2022-12-19 Nobuho Hashimoto , Shinya Takamaeda-Yamazaki

Hardware accelerators such as GPUs are required for real-time, low-latency inference with Deep Neural Networks (DNN). However, due to the inherent limits to the parallelism they can exploit, DNNs often under-utilize the capacity of today's…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-04-27 Aditya Dhakal , Sameer G. Kulkarni , K. K. Ramakrishnan

Recently, Graph Neural Networks (GNNs) have become state-of-the-art algorithms for analyzing non-euclidean graph data. However, to realize efficient GNN training is challenging, especially on large graphs. The reasons are many-folded: 1)…

Machine Learning · Computer Science 2022-08-17 Zhe Zhou , Cong Li , Xuechao Wei , Xiaoyang Wang , Guangyu Sun

With the development of deep neural network (DNN) enabled applications, achieving high hardware resource efficiency on diverse workloads is non-trivial in heterogeneous computing platforms. Prior works discuss dedicated architectures to…

Hardware Architecture · Computer Science 2026-04-14 Xingzhen Chen , Jinming Zhuang , Zhuoping Yang , Shixin Ji , Sarah Schultz , Zheng Dong , Weisong Shi , Peipei Zhou

Recent breakthroughs in Deep Neural Networks (DNNs) have fueled a growing demand for DNN chips. However, designing DNN chips is non-trivial because: (1) mainstream DNNs have millions of parameters and operations; (2) the large design space…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-12 Pengfei Xu , Xiaofan Zhang , Cong Hao , Yang Zhao , Yongan Zhang , Yue Wang , Chaojian Li , Zetong Guan , Deming Chen , Yingyan Lin

Latency and energy consumption are key metrics in the performance of deep neural network (DNN) accelerators. A significant factor contributing to latency and energy is data transfers. One method to reduce transfers or data is reusing data…

Hardware Architecture · Computer Science 2024-10-15 Michael Gilbert , Yannan Nellie Wu , Joel S. Emer , Vivienne Sze

Various processing-in-memory (PIM) accelerators based on various devices, micro-architectures, and interfaces have been proposed to accelerate deep neural networks (DNNs). How to deploy DNNs onto PIM-based accelerators is the key to explore…

Hardware Architecture · Computer Science 2024-11-15 Xiaotian Sun , Xinyu Wang , Wanqian Li , Yinhe Han , Xiaoming Chen

Dynamic GNN inference has exhibited effectiveness in High Energy Physics (HEP) experiments at High Luminosity Large Hadron Collider (HL-LHC) due to strong capability to model complex particle interactions in collision events. Future HEP…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-24 Davendra Maharaj , Tu Pham , Peter Meiring , Kyungmin Park , Sena Durgut , Cong Hao , Matteo Cremonesi

Spiking Neural Networks (SNNs) have emerged as a promising approach to improve the energy efficiency of machine learning models, as they naturally implement event-driven computations while avoiding expensive multiplication operations. In…

Neural and Evolutionary Computing · Computer Science 2024-10-31 Anagha Nimbekar , Prabodh Katti , Chen Li , Bashir M. Al-Hashimi , Amit Acharyya , Bipin Rajendran

Overlays have shown significant promise for field-programmable gate-arrays (FPGAs) as they allow for fast development cycles and remove many of the challenges of the traditional FPGA hardware design flow. However, this often comes with a…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-07-18 Mohamed S. Abdelfattah , David Han , Andrew Bitar , Roberto DiCecco , Shane OConnell , Nitika Shanker , Joseph Chu , Ian Prins , Joshua Fender , Andrew C. Ling , Gordon R. Chiu

Deformable convolution networks (DCNs) proposed to address the image recognition with geometric or photometric variations typically involve deformable convolution that convolves on arbitrary locations of input features. The locations change…

Hardware Architecture · Computer Science 2021-07-07 Dawen Xu , Cheng Chu , Cheng Liu , Ying Wang , Huawei Li , Xiaowei Li , Kwang-Ting Cheng

Ensembles of Deep Neural Networks (DNNs) have achieved qualitative predictions but they are computing and memory intensive. Therefore, the demand is growing to make them answer a heavy workload of requests with available computational…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-08-31 Pierrick Pochelu , Serge G. Petiton , Bruno Conche

For Human Action Recognition tasks (HAR), 3D Convolutional Neural Networks have proven to be highly effective, achieving state-of-the-art results. This study introduces a novel streaming architecture based toolflow for mapping such models…

Hardware Architecture · Computer Science 2024-03-05 Petros Toupas , Alexander Montgomerie-Corcoran , Christos-Savvas Bouganis , Dimitrios Tzovaras

Fault-Aware Training (FAT) has emerged as a highly effective technique for addressing permanent faults in DNN accelerators, as it offers fault mitigation without significant performance or accuracy loss, specifically at low and moderate…

Hardware Architecture · Computer Science 2023-04-26 Muhammad Abdullah Hanif , Muhammad Shafique

Deploying deep neural networks (DNNs) on those resource-constrained edge platforms is hindered by their substantial computation and storage demands. Quantized multi-precision DNNs, denoted as MP-DNNs, offer a promising solution for these…

Hardware Architecture · Computer Science 2024-10-10 Chuanning Wang , Chao Fang , Xiao Wu , Zhongfeng Wang , Jun Lin

Deformable Attention Transformers (DAT) have shown remarkable performance in computer vision tasks by adaptively focusing on informative image regions. However, their data-dependent sampling mechanism introduces irregular memory access…

Computer Vision and Pattern Recognition · Computer Science 2025-07-29 Wendong Mao , Mingfan Zhao , Jianfeng Guan , Qiwei Dong , Zhongfeng Wang

Processing Using Memory (PUM) accelerators have the potential to perform Deep Neural Network (DNN) inference by using arrays of memory cells as computation engines. Among various memory technologies, ReRAM crossbars show promising…

Hardware Architecture · Computer Science 2024-10-24 Mohammad Sabri , Marc Riera , Antonio González

Recent technological advances have proliferated the available computing power, memory, and speed of modern Central Processing Units (CPUs), Graphics Processing Units (GPUs), and Field Programmable Gate Arrays (FPGAs). Consequently, the…

Machine Learning · Computer Science 2021-02-18 Corey Lammie , Wei Xiang , Mostafa Rahimi Azghadi

In this paper, we present a novel technique to search for hardware architectures of accelerators optimized for end-to-end training of deep neural networks (DNNs). Our approach addresses both single-device and distributed pipeline and tensor…

Hardware Architecture · Computer Science 2024-04-24 Muhammad Adnan , Amar Phanishayee , Janardhan Kulkarni , Prashant J. Nair , Divya Mahajan