Related papers: Towards a Cryogenic CMOS-Memristor Neural Decoder …

CMOS technology and its continuous scaling have made electronics and computers accessible and affordable for almost everyone on the globe; in addition, they have enabled the solutions of a wide range of societal problems and applications.…

Recently, in-memory analog matrix computing (AMC) with nonvolatile resistive memory has been developed for solving matrix problems in one step, e.g., matrix inversion of solving linear systems. However, the analog nature sets up a barrier…

Realizing a quantum network will require long-lived quantum memories with optical interfaces incorporated into a scalable architecture. Color centers quantum emitters in diamond have emerged as a promising memory modality due to their…

A solid-state quantum computer with dipolar coupling between qubits is proposed. The qubits are formed by the low-lying states of an isolated acceptor in silicon. The system has the scalability inherent to spin-based solid state systems,…

Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to…

The new emerging non-volatile memory (NVM) devices known as memristors could be the promising candidate for future digital architecture, owing to their nanoscale size and its ability to integrate with the exciting CMOS technology. In this…

Quantum error-correcting codes (QECCs) can eliminate the negative effects of quantum noise, the major obstacle to the execution of quantum algorithms. However, realizing practical quantum error correction (QEC) requires resolving many…

The need to repeatedly shuttle around synaptic weight values from memory to processing units has been a key source of energy inefficiency associated with hardware implementation of artificial neural networks. Analog in-memory computing…

Efficient decoding to estimate error locations from outcomes of syndrome measurement is the prerequisite for quantum error correction. Decoding in presence of circuit-level noise including measurement errors should be considered in case of…

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation…

The attention mechanism is a key computing kernel of Transformers, calculating pairwise correlations across the entire input sequence. The computing complexity and frequent memory access in computing self-attention put a huge burden on the…

In memory computing (IMC) architectures for deep learning (DL) accelerators leverage energy-efficient and highly parallel matrix vector multiplication (MVM) operations, implemented directly in memory arrays. Such IMC designs have been…

Compute-in-memory (CiM) emerges as a promising solution to solve hardware challenges in artificial intelligence (AI) and the Internet of Things (IoT), particularly addressing the "memory wall" issue. By utilizing nonvolatile memory (NVM)…

Even if Application-Specific Integrated Circuits (ASIC) have proven to be a relevant choice for integrating inference at the edge, they are often limited in terms of applicability. In this paper, we demonstrate that an ASIC neural network…

In this work, we investigate the behavior of Al2O3/TiO2-x cross-point memristors in cryogenic environment. We report successful resistive switching of memristor devices from 300 K down to 1.5 K. The I-V curves exhibit negative differential…

Achieving scalable, fault-tolerant quantum computation requires quantum memory architectures that minimize error correction overhead while preserving coherence. This work presents a framework for high-dimensional qudit memory in…

Neutral atom quantum processors have emerged as a promising platform for scalable quantum information processing, offering high-fidelity operations and exceptional qubit scalability. A key challenge in realizing practical applications is…

Deep learning training involves a large number of operations, which are dominated by high dimensionality Matrix-Vector Multiplies (MVMs). This has motivated hardware accelerators to enhance compute efficiency, but where data movement and…

We developed a new front-end application specific integrated circuit (ASIC) for the upgrade of the Maia x-ray microprobe. The ASIC instruments 32 configurable front-end channels that perform either positive or negative charge amplification,…

Abstract: Bionic learning with fused sensing, memory and processing functions outperforms artificial neural networks running on silicon chips in terms of efficiency and footprint. However, digital hardware implementation of bionic learning…