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It has always been difficult to balance the accuracy and performance of ISSs. RTL simulators or systems such as gem5 are used to execute programs in a cycle-accurate manner but are often prohibitively slow. In contrast, functional…

Hardware Architecture · Computer Science 2020-05-26 Xuan Guo , Robert Mullins

Residue number systems (RNS) represent numbers by their remainders modulo a set of relatively prime numbers. This paper pro- poses an efficient hardware implementation of modular multiplication and of the modulo function (X(mod P)), based…

Hardware Architecture · Computer Science 2018-08-10 Danila Gorodecky , Tiziano Villa

Space Cyber-Physical Systems (S-CPS) such as spacecraft and satellites strongly rely on the reliability of onboard computers to guarantee the success of their missions. Relying solely on radiation-hardened technologies is extremely…

Systems and Control · Electrical Eng. & Systems 2024-01-12 Michael Rogenmoser , Yvan Tortorella , Davide Rossi , Francesco Conti , Luca Benini

-Residue Number System (RNS) is a valuable tool for fast and parallel arithmetic. It has a wide application in digital signal processing, fault tolerant systems, etc. In this work, we introduce the 3-moduli set {2^n, 2^{2n}-1, 2^{2n}+1} and…

Hardware Architecture · Computer Science 2009-01-09 Arash Hariri , K. Navi , Reza Rastegar

RISC-V processors encounter substantial challenges in deploying multi-precision deep neural networks (DNNs) due to their restricted precision support, constrained throughput, and suboptimal dataflow design. To tackle these challenges, a…

Hardware Architecture · Computer Science 2024-07-16 Chuanning Wang , Chao Fang , Xiao Wu , Zhongfeng Wang , Jun Lin

RISC-V provides a flexible and scalable platform for applications ranging from embedded devices to high-performance computing clusters. Particularly, its RISC-V Vector Extension (RVV) becomes of interest for the acceleration of AI…

Machine Learning · Computer Science 2025-08-20 Federico Nicolas Peccia , Frederik Haxel , Oliver Bringmann

To reduce the area of RISC-V Vector extension (RVV) in small processors, the authors are considering one simple modification: reduce the number of registers in the vector register file. The standard 'V' extension requires 32 vector…

Hardware Architecture · Computer Science 2024-10-14 Eino Jacobs , Dmitry Utyansky , Muhammad Hassan , Thomas Roecker

The rapid development of RISC-V instruction set architecture presents new opportunities and challenges for software developers. Is it sufficient to simply recompile high-performance software optimized for x86-64 onto RISC-V CPUs? Are…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-06-17 Anna Pirova , Anastasia Vodeneeva , Konstantin Kovalev , Alexander Ustinov , Evgeny Kozinov , Alexey Liniov , Valentin Volokitin , Iosif Meyerov

Quantum Arithmetic faces limitations such as noise and resource constraints in the current Noisy Intermediate Scale Quantum (NISQ) era quantum computers. We propose using Distributed Quantum Computing (DQC) to overcome these limitations by…

Quantum Physics · Physics 2024-06-11 Bhaskar Gaur , Travis S. Humble , Himanshu Thapliyal

Achieving high accuracy, while maintaining good energy efficiency, in analog DNN accelerators is challenging as high-precision data converters are expensive. In this paper, we overcome this challenge by using the residue number system (RNS)…

Hardware Architecture · Computer Science 2023-06-19 Cansu Demirkiran , Rashmi Agrawal , Vijay Janapa Reddi , Darius Bunandar , Ajay Joshi

Inspired by recent findings on the fractal geometry of language, we introduce Recursive INference Scaling (RINS) as a complementary, plug-in recipe for scaling inference time in language and multimodal systems. RINS is a particular form of…

Artificial Intelligence · Computer Science 2025-05-09 Ibrahim Alabdulmohsin , Xiaohua Zhai

Integrating cryptographic accelerators into modern CPU architectures presents unique microarchitectural challenges, particularly when extending instruction sets with complex and multistage operations. Hardware-assisted cryptographic…

Hardware Architecture · Computer Science 2025-08-29 Alperen Bolat , Sakir Sezer , Kieran McLaughlin , Henry Hui

FREESS is a free, interactive simulator that illustrates instruction-level parallelism in a RISC-V-inspired superscalar processor. Based on an extended version of Tomasulo's algorithm, FREESS is intended as a hands-on educational tool for…

Hardware Architecture · Computer Science 2025-06-10 Roberto Giorgi

Nowadays, various memory-hungry applications like machine learning algorithms are knocking "the memory wall". Toward this, emerging memories featuring computational capacity are foreseen as a promising solution that performs data process…

Hardware Architecture · Computer Science 2023-03-28 Jia-Hui Su , Chen-Hua Lu , Jenq Kuen Lee , Andrea Coluccio , Fabrizio Riente , Marco Vacca , Marco Ottavi , Kuan-Hsun Chen

The rise of hardware accelerators with custom instructions necessitates custom compiler backends supporting these accelerators. This study provides detailed analyses of LLVM and its RISC-V backend, supplemented with case studies providing…

Hardware Architecture · Computer Science 2023-10-31 Eymen Ünay , Bora İnan , Emrecan Yiğit

Neural Networks (NNs) have been widely adopted due to their outstanding efficacy and adaptability across computer vision and deep learning applications. The optimization of NNs is necessary to enable their deployment on energy constrained…

Hardware Architecture · Computer Science 2026-05-12 Pragun Jaswal , L. Hemanth Krishna , B. Srinivasu

For years, the open-source RISC-V instruction set has been driving innovation in processor design, spanning from high-end cores to low-cost or low-power cores. After a decade of evolution, RISC architectures are now as mature as the CISC…

Hardware Architecture · Computer Science 2024-06-24 Juliette Pottier , Thomas Nieddu , Bertrand Le Gal , Sébastien Pillement , Maria Méndez Real

This technical note presents a algorithmic approach for generating optimal sets of co-prime moduli within specified integer ranges. The proposed method addresses the challenge of balancing moduli bit-lengths while maximizing the dynamic…

Other Computer Science · Computer Science 2026-03-26 Danila Gorodecky

Symbolic execution is a powerful technique for analyzing the behavior of software yet scalability remains a challenge due to state explosion in control and data flow. Existing tools typically aim at managing control flow internally, often…

Programming Languages · Computer Science 2025-07-15 Anna Bolotina , Christoph M. Kirsch , Stefanie Muroya Lei , Matthias Pleschinger

Reciprocal recommender systems (RRSs) are crucial in online two-sided matching platforms, such as online job or dating markets, as they need to consider the preferences of both sides of the match. The concentration of recommendations to a…

Information Retrieval · Computer Science 2024-12-02 Kento Nakada , Kazuki Kawamura , Ryosuke Furukawa