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The rapid progress and advancement in electronic chips technology provide a variety of new implementation options for system engineers. The choice varies between the flexible programs running on a general-purpose processor (GPP) and the…

Hardware Architecture · Computer Science 2019-04-11 Issam Damaj

A current trend in HPC systems is the utilization of architectures with SIMD or vector extensions to exploit data parallelism. There are several ways to take advantage of such modern vector architectures, each with a different impact on the…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-11-05 Marc Blancafort , Roger Ferrer , Guillaume Houzeaux , Marta Garcia-Gasulla , Filippo Mantovani

Ring-Learning-with-Errors (RLWE) has emerged as the foundation of many important techniques for improving security and privacy, including homomorphic encryption and post-quantum cryptography. While promising, these techniques have received…

Processing computer vision applications (CVA) on mobile devices is challenging due to limited battery life and computing power. While cloud-based remote processing of CVA offers abundant computational resources, it introduces latency issues…

Networking and Internet Architecture · Computer Science 2025-01-09 Marcelo V. B. da Silva , Maria Barbosa , Anderson Queiroz , Kelvin L. Dias

Whilst RISC-V has grown phenomenally quickly in embedded computing, it is yet to gain significant traction in High Performance Computing (HPC). However, as we move further into the exascale era, the flexibility offered by RISC-V has the…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-06-19 Nick Brown , Maurice Jamieson

Single-issue processor cores are very energy efficient but suffer from the von Neumann bottleneck, in that they must explicitly fetch and issue the loads/storse necessary to feed their ALU/FPU. Each instruction spent on moving data is a…

Hardware Architecture · Computer Science 2020-04-02 Fabian Schuiki , Florian Zaruba , Torsten Hoefler , Luca Benini

Software-hardware co-design solutions for decimal computation can provide several Pareto points to development of embedded systems in terms of hardware cost and performance. This paper demonstrates how to accurately evaluate such co-design…

Hardware Architecture · Computer Science 2020-03-12 Riaz-ul-haque Mian , Michihiro Shintani , Michiko Inoue

Whilst RISC-V has become popular in fields such as embedded computing, it is yet to find mainstream success in High Performance Computing (HPC). However, the 64-core RISC-V Sophon SG2042 is a potential game changer as it provides a…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-02-17 Nick Brown , Christopher Day

Serverless computing is gaining traction as an attractive model for the deployment of a multitude of workloads in the cloud. Designing and building effective resource management solutions for any computing environment requires extensive…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-09-20 Anupama Mampage , Rajkumar Buyya

Optimization of applications for supercomputers of the highest performance class requires parallelization at multiple levels using different techniques. In this contribution we focus on parallelization of particle physics simulations…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-01-23 Nils Meyer , Peter Georg , Dirk Pleiter , Stefan Solbrig , Tilo Wettig

Ensuring a continuous and growing influx of skilled chip designers and a smooth path from education to innovation are key goals for several national and international "Chips Acts". Silicon democratization can greatly benefit from end-to-end…

With the increasing interest in neuromorphic computing, designers of embedded systems face the challenge of efficiently simulating such platforms to enable architecture design exploration early in the development cycle. Executing artificial…

Hardware Architecture · Computer Science 2021-12-28 Melvin Galicia , Farhad Merchant , Rainer Leupers

Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications. In this tutorial paper, we outline the main architectural design principles behind fully digital neuromorphic…

Hardware Architecture · Computer Science 2025-12-02 Amirreza Yousefzadeh

RISC-V is a recently developed open instruction set architecture gaining a lot of attention. To achieve a lasting security on these systems and design efficient countermeasures, a better understanding of vulnerabilities to novel and…

Cryptography and Security · Computer Science 2023-07-25 Loïc Buckwell , Olivier Gilles , Daniel Gracia Pérez , Nikolai Kosmatov

This paper introduces a computer architecture, where part of the instruction set architecture (ISA) is implemented on small highly-integrated field-programmable gate arrays (FPGAs). Small FPGAs inside a general-purpose processor (CPU) can…

Hardware Architecture · Computer Science 2022-08-23 Philippos Papaphilippou , Myrtle Shah

Address translation and protection play important roles in today's processors, supporting multiprocessing and enforcing security. Historically, the design of the address translation mechanisms has been closely tied to the instruction set.…

Hardware Architecture · Computer Science 2019-05-17 Xuan Guo , Robert Mullins

The emergence and rapid development of the open RISC-V instruction set architecture opens up new horizons on the way to efficient devices, ranging from existing low-power IoT boards to future high-performance servers. The effective use of…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-04-04 Evgeny Kozinov , Evgeny Vasiliev , Andrey Gorshkov , Valentina Kustikova , Artem Maklaev , Valentin Volokitin , Iosif Meyerov

Embedded systems are pervasively used in many fields nowadays. In mixed-criticality environments (automotive, industry 4.0, drones, etc.) they need to run real-time applications with certain time and safety constraints alongside a rich…

Cryptography and Security · Computer Science 2021-11-05 Flavia Caforio , Pierpaolo Iannicelli , Michele Paolino , Daniel Raho

This paper makes the case for a single-ISA heterogeneous computing platform, AISC, where each compute engine (be it a core or an accelerator) supports a different subset of the very same ISA. An ISA subset may not be functionally complete,…

Hardware Architecture · Computer Science 2018-03-20 Alexandra Ferreron , Jesus Alastruey-Benede , Dario Suarez-Gracia , Ulya R. Karpuzcu

Today edge devices commonly connect to the cloud to use its storage and compute capabilities. This leads to security and privacy concerns about user data. Homomorphic Encryption (HE) is a promising solution to address the data privacy…

Cryptography and Security · Computer Science 2023-02-15 Zahra Azad , Guowei Yang , Rashmi Agrawal , Daniel Petrisko , Michael Taylor , Ajay Joshi