Related papers: Delay-Optimum Adder Circuits with Linear Size
We study parallel algorithms for addition of numbers having finite representation in a positional numeration system defined by a base $\beta$ in $\mathbb{C}$ and a finite digit set $\mathcal{A}$ of contiguous integers containing $0$. For a…
Given a sequence of integers, we want to find a longest increasing subsequence of the sequence. It is known that this problem can be solved in $O(n \log n)$ time and space. Our goal in this paper is to reduce the space consumption while…
Software methods introduced for automated design of approximate implementations of arithmetic circuits rely on fast and accurate evaluation of approximate candidate implementations. To accelerate the evaluation of circuit error, we propose…
Inaccurate circuits make possible the conservation of limited resources, such as energy. But effective design of such circuits requires an understanding of resulting tradeoffs between accuracy and design parameters, such as voltages and…
We optimize the area and latency of Shor's factoring while simultaneously improving fault tolerance through: (1) balancing the use of ancilla generators, (2) aggressive optimization of error correction, and (3) tuning the core adder…
This paper deals with the problem of increasing the minimum distance of a linear code by adding one or more columns to the generator matrix. Several methods to compute extensions of linear codes are presented. Many codes improving the…
The paper introduces a new technique for compressing Binary Decision Diagrams in those cases where random access is not required. Using this technique, compression and decompression can be done in linear time in the size of the BDD and…
Practically good error-correcting codes should have good parameters and efficient decoding algorithms. Some algebraically defined good codes such as cyclic codes, Reed-Solomon codes, and Reed-Muller codes have nice decoding algorithms.…
Multiplier circuits play an important role in reversible computation, which is helpful in diverse areas such as low power CMOS design, optical computing, DNA computing and bioinformatics. Here we propose a new reversible multiplier circuit…
In this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive…
Using a new general approach to limits in optical structures that counts orthogonal waves generated by scattering, we derive an upper limit to the number of bits of delay possible in one-dimensional slow light structures that are based on…
Let $A(n,d,w)$ be the largest possible size of an $(n,d,w)$ constant-weight binary code. By adding new constraints to Delsarte linear programming, we obtain twenty three new upper bounds on $A(n,d,w)$ for $n \leq 28$. The used techniques…
Given a polygon representing a transportation network together with a point p in its interior, we aim to extend the network by inserting a line segment, called a feed-link, which connects p to the boundary of the polygon. Once a feed link…
We consider the problem of detecting a cycle in a directed graph that grows by arc insertions, and the related problems of maintaining a topological order and the strong components of such a graph. For these problems, we give two…
We present the first linear lower bound for the number of bits required to be accessed in the worst case to increment an integer in an arbitrary space- optimal binary representation. The best previously known lower bound was logarithmic. It…
We study codes that can detect the exact number of deletions and insertions in concatenated binary strings. We construct optimal codes for the case of detecting up to $\del$ deletions. We prove the optimality of these codes by deriving a…
We construct new linear codes with high minimum distance d. In at least 12 cases these codes improve the minimum distance of the previously known best linear codes for fixed parameters n,k. Among these new codes there is an optimal ternary…
We present an arithmetic circuit performing constant modular addition having $\mathcal{O}(n)$ depth of Toffoli gates and using a total of $n+3$ qubits. This is an improvement by a factor of two compared to the width of the state-of-the-art…
The state of the art of quantum circuits using the ripple-carry strategy for the addition and comparison of two n-bit numbers is presented, as well as optimizations in the Clifford+T gate set, both in terms of CNOT-depth and T-depth, or…
Future 5G systems will need to support ultra-reliable low-latency communications scenarios. From a latency-reliability viewpoint, it is inefficient to rely on average utility-based system design. Therefore, we introduce the notion of…