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The rapid advancements in artificial intelligence (AI), particularly the Large Language Models (LLMs), have profoundly affected our daily work and communication forms. However, it is still a challenge to deploy LLMs on resource-constrained…

Hardware Architecture · Computer Science 2025-03-03 Mingqiang Huang , Ao Shen , Kai Li , Haoxiang Peng , Boyu Li , Yupeng Su , Hao Yu

FPGAs have been shown to be a promising platform for deploying Quantised Neural Networks (QNNs) with high-speed, low-latency, and energy-efficient inference. However, the complexity of modern deep-learning models limits the performance on…

Hardware Architecture · Computer Science 2025-11-06 Changhong Li , Biswajit Basu , Shreejith Shanker

3D reconstruction from videos has become increasingly popular for various applications, including navigation for autonomous driving of robots and drones, augmented reality (AR), and 3D modeling. This task often combines traditional…

Hardware Architecture · Computer Science 2022-12-19 Nobuho Hashimoto , Shinya Takamaeda-Yamazaki

With the growing number of data-intensive workloads, GPU, which is the state-of-the-art single-instruction-multiple-thread (SIMT) processor, is hindered by the memory bandwidth wall. To alleviate this bottleneck, previously proposed…

Hardware Architecture · Computer Science 2021-03-12 Xinfeng Xie , Peng Gu , Yufei Ding , Dimin Niu , Hongzhong Zheng , Yuan Xie

Advances in life sciences over the last few decades have lead to the generation of a huge amount of biological data. Computing research has become a vital part in driving biological discovery where analysis and categorization of biological…

Computational Engineering, Finance, and Science · Computer Science 2014-03-31 S. M. Vidanagamachchi , S. D. Dewasurendra , R. G. Ragel , M. Niranjan

Recent advances in reprogrammable hardware (e.g., FPGAs) and memory technology (e.g., DDR4, HBM) promise to solve performance problems inherent to graph processing like irregular memory access patterns on traditional hardware (e.g., CPU).…

Hardware Architecture · Computer Science 2021-04-19 Jonas Dann , Daniel Ritter , Holger Fröning

Probabilistic bits (p-bits) offer an energy-efficient hardware abstraction for stochastic optimization; however, existing p-bit-based simulated annealing accelerators suffer from poor scalability and limited support for fully connected…

Hardware Architecture · Computer Science 2026-02-19 Naoya Onizawa , Taiga Kubuta , Duckgyu Shin , Takahiro Hanyu

The increasing number of processing elements and decreas- ing memory to core ratio in modern high-performance platforms makes efficient strong scaling a key requirement for numerical algorithms. In order to achieve efficient scalability on…

Distributed, Parallel, and Cluster Computing · Computer Science 2015-01-14 Michael Lange , Gerard Gorman , Michele Weiland , Lawrence Mitchell , James Southern

Deep neural networks (DNNs) are a type of artificial intelligence models that are inspired by the structure and function of the human brain, designed to process and learn from large amounts of data, making them particularly well-suited for…

Hardware Architecture · Computer Science 2024-07-18 Alireza Senobari , Jafar Vafaei , Omid Akbari , Christian Hochberger , Muhammad Shafique

Matrix multiplication is a foundational operation in scientific computing and machine learning, yet its computational complexity makes it a significant bottleneck for large-scale applications. The shift to parallel architectures, primarily…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-07-30 Mufakir Qamar Ansari , Mudabir Qamar Ansari

Spiking Neural Networks (SNNs), with brain-inspired structure using discrete spikes instead of continuous activations, are gaining attention for their efficient processing on neuromorphic chips. While current SNN hardware accelerators often…

Hardware Architecture · Computer Science 2026-01-30 Tenglong Li , Jindong Li , Guobin Shen , Dongcheng Zhao , Qian Zhang , Yi Zeng

The rapid growth of AI-based Internet-of-Things applications increased the demand for high-performance edge processing engines on a low-power budget and tight area constraints. As a consequence, vector processor architectures, traditionally…

Large-scale linear programs (LPs) arise in many decision systems, including ranking, allocation, and matching problems that must be solved repeatedly at massive scale. Prior work such as ECLIPSE and LinkedIn's open-source DuaLip showed that…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-06 Gregory Dexter , Aida Rahmattalabi , Sanjana Garg , Qinquan Song , Ruby Tu , Yuan Gao , Yi Zhang , Zhipeng Wang , Rahul Mazumder

Mixed-precision neural networks (MPNNs) that enable the use of just enough data width for a deep learning task promise significant advantages of both inference accuracy and computing overhead. FPGAs with fine-grained reconfiguration…

Hardware Architecture · Computer Science 2023-08-23 Erjing Luo , Haitong Huang , Cheng Liu , Guoyu Li , Bing Yang , Ying Wang , Huawei Li , Xiaowei Li

The increasing demand for on-device intelligence in Edge AI and TinyML applications requires the efficient execution of modern Convolutional Neural Networks (CNNs). While lightweight architectures like MobileNetV2 employ Depthwise Separable…

Hardware Architecture · Computer Science 2025-11-27 Muhammed Yildirim , Ozcan Ozturk

GPUs have been widely used to accelerate computations exhibiting simple patterns of parallelism - such as flat or two-level parallelism - and a degree of parallelism that can be statically determined based on the size of the input dataset.…

Distributed, Parallel, and Cluster Computing · Computer Science 2016-11-18 Hancheng Wu , Da Li , Michela Becchi

This paper introduces TINA, a novel framework for implementing non Neural Network (NN) signal processing algorithms on NN accelerators such as GPUs, TPUs or FPGAs. The key to this approach is the concept of mapping mathematical and logic…

Performance · Computer Science 2024-08-30 Christiaan Boerkamp , Steven van der Vlugt , Zaid Al-Ars

Systolic arrays have been widely used for accelerating HPC and deep learning applications. There is a plethora of previous works on the performance tuning of systolic arrays, but usually based on a number of oversimplified assumptions…

Hardware Architecture · Computer Science 2021-11-30 Jie Wang , Jason Cong

The scale invariant feature transform (SIFT) algorithm is considered a classical feature extraction algorithm within the field of computer vision. SIFT keypoint descriptor matching is a computationally intensive process due to the amount of…

Computer Vision and Pattern Recognition · Computer Science 2020-12-18 Luka Daoud , Muhammad Kamran Latif , H S. Jacinto , Nader Rafla

The fast proliferation of extreme-edge applications using Deep Learning (DL) based algorithms required dedicated hardware to satisfy extreme-edge applications' latency, throughput, and precision requirements. While inference is achievable…

Hardware Architecture · Computer Science 2022-04-26 Yvan Tortorella , Luca Bertaccini , Davide Rossi , Luca Benini , Francesco Conti
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