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The time required for training the neural networks increases with size, complexity, and depth. Training model parameters by backpropagation inherently creates feedback loops. These loops hinder efficient pipelining and scheduling of the…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-12-30 Nanda K. Unnikrishnan , Keshab K. Parhi

Spurred by widening gap between data processing speed and data communication speed in Von-Neumann computing architectures, some bioinformatic applications have harnessed the computational power of Processing-in-Memory (PIM) platforms.…

Hardware Architecture · Computer Science 2020-08-17 Shaahin Angizi , Naima Ahmed Fahmi , Wei Zhang , Deliang Fan

The need to efficiently execute different Deep Neural Networks (DNNs) on the same computing platform, coupled with the requirement for easy scalability, makes Multi-Chip Module (MCM)-based accelerators a preferred design choice. Such an…

Hardware Architecture · Computer Science 2024-08-26 Abhijit Das , Enrico Russo , Maurizio Palesi

The utilization of large-scale neural networks on Processing-In-Memory (PIM) accelerators encounters challenges due to constrained on-chip memory capacity. To tackle this issue, current works explore model compression algorithms to reduce…

Hardware Architecture · Computer Science 2024-04-18 Chenyu Wang , Zhen Dong , Daquan Zhou , Zhenhua Zhu , Yu Wang , Jiashi Feng , Kurt Keutzer

Approximate nearest neighbor search (ANNS) is essential for applications like recommendation systems and retrieval-augmented generation (RAG) but is highly I/O-intensive and memory-demanding. CPUs face I/O bottlenecks, while GPUs are…

Performance · Computer Science 2025-08-27 Mingkai Chen , Tianhua Han , Cheng Liu , Shengwen Liang , Kuai Yu , Lei Dai , Ziming Yuan , Ying Wang , Lei Zhang , Huawei Li , Xiaowei Li

Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and…

Hardware Architecture · Computer Science 2022-06-03 Batel Oved , Orian Leitersdorf , Ronny Ronen , Shahar Kvatinsky

Sequence alignment is a memory bound computation whose performance in modern systems is limited by the memory bandwidth bottleneck. Processing-in-memory architectures alleviate this bottleneck by providing the memory with computing…

Hardware Architecture · Computer Science 2023-03-28 Safaa Diab , Amir Nassereldine , Mohammed Alser , Juan Gómez-Luna , Onur Mutlu , Izzat El Hajj

Resistive Random-Access Memory (RRAM) is well-suited to accelerate neural network (NN) workloads as RRAM-based Processing-in-Memory (PIM) architectures natively support highly-parallel multiply-accumulate (MAC) operations that form the…

Hardware Architecture · Computer Science 2022-11-11 Aditya Manglik , Minesh Patel , Haiyu Mao , Behzad Salami , Jisung Park , Lois Orosa , Onur Mutlu

Processing-in-DRAM (DRAM-PIM) has emerged as a promising technology for accelerating memory-intensive operations in modern applications, such as Large Language Models (LLMs). Despite its potential, current software stacks for DRAM-PIM face…

Hardware Architecture · Computer Science 2025-06-03 Yongwon Shin , Dookyung Kang , Hyojin Sung

Demand for data-intensive workloads and confidential computing are the prominent research directions shaping the future of cloud computing. Computer architectures are evolving to accommodate the computing of large data better. Protecting…

Cryptography and Security · Computer Science 2023-04-11 Kha Dinh Duy , Hojoon Lee

Hashmaps are widely utilized data structures in many applications to perform a probe on key-value pairs. However, their performance tends to degrade with the increase in the dataset size, which leads to expensive off-chip memory accesses to…

Hardware Architecture · Computer Science 2023-07-03 Akhil Shekar , Morteza Baradaran , Sabiha Tajdari , Kevin Skadron

In this article, we introduce an instruction set architecture (ISA) for processing-in-memory (PIM) based deep neural network (DNN) accelerators. The proposed ISA is for DNN inference on PIM-based architectures. It is assumed that the…

Programming Languages · Computer Science 2023-08-15 Xiaoming Chen

Graph neural networks (GNNs) have gained significant interest for applications such as citation network analysis and drug discovery due to their ability to apply machine learning techniques on graph-structured data. GNNs typically employ a…

Hardware Architecture · Computer Science 2026-05-28 Siddhartha Raman Sundara Raman , Lizy John , Jaydeep P. Kulkarni

The last decade has witnessed growth in the computational requirements for training deep neural networks. Current approaches (e.g., data/model parallelism, pipeline parallelism) parallelize training tasks onto multiple devices. However,…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-07-09 Siyu Wang , Yi Rong , Shiqing Fan , Zhen Zheng , LanSong Diao , Guoping Long , Jun Yang , Xiaoyong Liu , Wei Lin

Processing-in-memory architectures have been regarded as a promising solution for CNN acceleration. Existing PIM accelerator designs rely heavily on the experience of experts and require significant manual design overhead. Manual design…

Hardware Architecture · Computer Science 2024-02-29 Wanqian Li , Xiaotian Sun , Xinyu Wang , Lei Wang , Yinhe Han , Xiaoming Chen

Processing In Memory (PIM) accelerators are promising architecture that can provide massive parallelization and high efficiency in various applications. Such architectures can instantaneously provide ultra-fast operation over extensive…

Hardware Architecture · Computer Science 2022-07-26 Kazi Abu Zubair , Sumit Kumar Jha , David Mohaisen , Clayton Hughes , Amro Awad

DL inference queries play an important role in diverse internet services and a large fraction of datacenter cycles are spent on processing DL inference queries. Specifically, the matrix-matrix multiplication (GEMM) operations of…

Hardware Architecture · Computer Science 2020-12-02 Benjamin Y. Cho , Jeageun Jung , Mattan Erez

Compute in-memory (CIM) is a promising technique that minimizes data transport, the primary performance bottleneck and energy cost of most data intensive applications. This has found wide-spread adoption in accelerating neural networks for…

Hardware Architecture · Computer Science 2020-08-18 Brian Crafton , Samuel Spetalnick , Gauthaman Murali , Tushar Krishna , Sung-Kyu Lim , Arijit Raychowdhury

Deep neural networks (DNNs) have been shown to outperform conventional machine learning algorithms across a wide range of applications, e.g., image recognition, object detection, robotics, and natural language processing. However, the high…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-04-23 Ye Yu , Yingmin Li , Shuai Che , Niraj K. Jha , Weifeng Zhang

Deep neural networks are a promising solution for applications that solve problems based on learning data sets. DNN accelerators solve the processing bottleneck as a domain-specific processor. Like other hardware solutions, there must be…

Hardware Architecture · Computer Science 2022-11-08 Midia Reshadi , David Gregg
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