Related papers: High-Resolution, Multi-Channel FPGA-Based Time-to-…
Time interleaved analog-to-digital conversion (TIADC) based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different…
High-speed high-resolution Analog-to-Digital Conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in…
This paper proposes a high-precision time measurement method based on digital frequency-domain phase-fitting (DFPF) by using the digitized nuclear pulses. The averaging effect inherent in the frequency-domain cross-correlation and…
We demonstrate a 10-GHz bandwidth digitizer with 7-effective bits of resolution and 52dB SFDR, using photonic time stretch technique. To the best of our knowledge, this is the highest resolution analog-to-digital converter (ADC) of the same…
Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting…
The aim of this study is to design and evaluate a simple free running Analog-Digital Converter (ADC) based on the Field Programmable Gate Array (FPGA) device to accomplish the energy and position readout of the silicon photomultiplier…
We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of $100\times100~\mu \text{m}^2$, where the sensors are Low Gain…
The characterization of laboratory plasma instabilities, magnetic reconnection and turbulence associated phenomena, require the simultaneous signal sampling from arrays of magnetic sensors (hundreds or even thousands) to obtain spatial…
In most digital-to-time converter (DTC) based applications, apart from maintaining low integral non-linearity (INL), it is also required of the system to achieve a wide frequency translation range. To achieve this performance, we present a…
With the new generation of the RPC, it is possible to work with induced signals of hundreds $\mu V$, hence the front-end electronics is an important and delicate part of the detector in order to get a detectable signal. The electronic chain…
Time-domain reflectometry (TDR) is an established means of measuring impedance inhomogeneity of a variety of waveguides, providing critical data necessary to characterize and optimize the performance of high-bandwidth computational and…
Development of readout electronics for Time Projection Chamber for a Linear Collider is ongoing under stringent requirements on high channel density, lowest possible power consumption and small material budget. In the studied TPC readout…
Intrinsic nonlinearity in FPGA-based time-to-digital converters (TDCs) is often treated as a calibration issue and evaluated mainly through post-correction metrics. In quantum key distribution (QKD), however, raw delay-line nonuniformity…
In TDC testing or timing system implementation tasks, it is often desirable to generate signal pulses with fine adjustable time intervals. In delay cell-based schemes, the time adjustment steps are limited by the propagation delays of the…
The SAMpler for PICosecond time (SAMPIC) chip has been designed by a collaboration including CEA/IRFU/SEDI, Saclay and CNRS/LAL/SERDI, Orsay. It benefits from both the quick response of a time to digital converter and the versatility of a…
We have developed a completely new type of general-purpose CCD data acquisition system which enables one to drive any type of CCD using any type of clocking mode. A CCD driver system widely used before consisted of an analog multiplexer…
In recent years, high speed and high resolution analog-to-digital converter (ADC) is widely employed in many physical experiments, especially in high precision time and charge measurement. The rapid increasing amount of digitized data…
We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…
- This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage…
This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion…