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Stochastic computing (SC) offers hardware simplicity but suffers from low throughput, while high-throughput Digital Computing-in-Memory (DCIM) is bottlenecked by costly adder logic for matrix-vector multiplication (MVM). To address this…

Hardware Architecture · Computer Science 2026-01-13 Kunming Shao , Liang Zhao , Jiangnan Yu , Zhipeng Liao , Xiaomeng Wang , Yi Zou , Tim Kwang-Ting Cheng , Chi-Ying Tsui

Compute-in-memory (CIM) techniques are widely employed in energy-efficient artificial intelligent (AI) processors. They alleviate power and latency bottlenecks caused by extensive data movements between compute and storage units. To extend…

Hardware Architecture · Computer Science 2025-12-15 Jianyi Yu , Tengxiao Wang , Yuxuan Wang , Xiang Fu , Fei Qiao , Ying Wang , Rui Yuan , Liyuan Liu , Cong Shi

Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference. However, a certain amount of digital post-processing is required to deal with circuit mismatches and non-idealities…

Hardware Architecture · Computer Science 2024-07-10 Elena Ferro , Athanasios Vasilopoulos , Corey Lammie , Manuel Le Gallo , Luca Benini , Irem Boybat , Abu Sebastian

Deep learning-based recommendation models (DLRMs) are widely deployed in commercial applications to enhance user experience. However, the large and sparse embedding layers in these models impose substantial memory bandwidth bottlenecks due…

Hardware Architecture · Computer Science 2025-09-16 Yu-Hong Lai , Chieh-Lin Tsai , Wen Sheng Lim , Han-Wen Hu , Tei-Wei Kuo , Yuan-Hao Chang

Write disturbance error (WDE) appears as a serious reliability problem preventing phase-change memory (PCM) from general commercialization, and therefore several studies have been proposed to mitigate WDEs. Verify-and-correction (VnC)…

Hardware Architecture · Computer Science 2022-08-10 Hyokeun Lee , Seungyong Lee , Byeongki Song , Moonsoo Kim , Seokbo Shim , Hyuk-Jae Lee , Hyun Kim

In this work, we employ neural architecture search (NAS) to enhance the efficiency of deploying diverse machine learning (ML) tasks on in-memory computing (IMC) architectures. Initially, we design three fundamental components inspired by…

Machine Learning · Computer Science 2024-06-12 Md Hasibul Amin , Mohammadreza Mohammadi , Ramtin Zand

In-Memory Acceleration (IMA) promises major efficiency improvements in deep neural network (DNN) inference, but challenges remain in the integration of IMA within a digital system. We propose a heterogeneous architecture coupling 8 RISC-V…

Hardware Architecture · Computer Science 2021-09-06 Gianmarco Ottavi , Geethan Karunaratne , Francesco Conti , Irem Boybat , Luca Benini , Davide Rossi

At the edge, there is a high level of similarity in computing. One approach that has been proposed to enhance the efficiency of edge computing is computation reuse, which eliminates redundant computations. Edge computing is integrated with…

Networking and Internet Architecture · Computer Science 2025-02-05 Atiyeh Javaheri , Ali Bohlooli , Kamal Jamshidi

Neural Networks (NNs) have been widely adopted due to their outstanding efficacy and adaptability across computer vision and deep learning applications. The optimization of NNs is necessary to enable their deployment on energy constrained…

Hardware Architecture · Computer Science 2026-05-12 Pragun Jaswal , L. Hemanth Krishna , B. Srinivasu

The surge in AI usage demands innovative power reduction strategies. Novel Compute-in-Memory (CIM) architectures, leveraging advanced memory technologies, hold the potential for significantly lowering energy consumption by integrating…

Signal Processing · Electrical Eng. & Systems 2024-05-14 José Cubero-Cascante , Arunkumar Vaidyanathan , Rebecca Pelke , Lorenzo Pfeifer , Rainer Leupers , Jan Moritz Joseph

In memory computing (IMC) architectures for deep learning (DL) accelerators leverage energy-efficient and highly parallel matrix vector multiplication (MVM) operations, implemented directly in memory arrays. Such IMC designs have been…

Emerging Technologies · Computer Science 2024-08-14 Arkapravo Ghosh , Hemkar Reddy Sadana , Mukut Debnath , Panthadip Maji , Shubham Negi , Sumeet Gupta , Mrigank Sharad , Kaushik Roy

With the rapid advent of generative models, efficiently deploying these models on specialized hardware has become critical. Tensor Processing Units (TPUs) are designed to accelerate AI workloads, but their high power consumption…

Hardware Architecture · Computer Science 2025-03-04 Zhantong Zhu , Hongou Li , Wenjie Ren , Meng Wu , Le Ye , Ru Huang , Tianyu Jia

Ternary large language models (LLMs), which utilize ternary precision weights and 8-bit activations, have demonstrated competitive performance while significantly reducing the high computational and memory requirements of full-precision…

Hardware Architecture · Computer Science 2025-06-03 Akul Malhotra , Sumeet Kumar Gupta

RRAM-based in-memory computing (IMC) offers high energy efficiency but suffers from conductance drift that severely degrades long-term accuracy. Existing approaches including retraining, noise-aware training, and Batch Normalization…

Hardware Architecture · Computer Science 2026-03-30 Weirong Dong , Kai Zhou , Zhen Kong , Zhengke Yang , Quan Cheng , Haoyuan Li , Junkai Huang , Jun Lan , Yida Li , Masanori Hashimoto , Longyang Lin

Voltage underscaling below the nominal level is an effective solution for improving energy efficiency in digital circuits, e.g., Field Programmable Gate Arrays (FPGAs). However, further undervolting below a safe voltage level and without…

Hardware Architecture · Computer Science 2019-04-01 Behzad Salami , Osman S. Unsal , Adrian Cristal Kestelman

Traditional machine learning depends on high-precision arithmetic and near-ideal hardware assumptions, which is increasingly challenged by variability in aggressively scaled semiconductor devices. Compute-in-memory (CIM) architectures…

Emerging Technologies · Computer Science 2026-04-15 William Youngwoo Chung , Hamza Errahmouni Barkam , Tamoghno Das , Mohsen Imani

Binary matrix-vector multiplication (BMVM) is a key operation in post-quantum cryptography schemes like the Classic McEliece cryptosystem. Conventional computing architectures incur significant energy efficiency loss due to data movement of…

Emerging Technologies · Computer Science 2025-07-15 Hao Yue , Yihao Chen , Tianhang Liang , Xiangrui Li , Xin Kong , Zhelong Jiang , Zhigang Li , Gang Chen , Huaxiang Lu

Large language models (LLMs) can generate programs that pass unit tests, but passing tests does not guarantee reliable runtime behavior. We find that different correct solutions to the same task can show very different memory and…

Compute-In-Memory (CIM) systems, particularly those utilizing ReRAM and memristive technologies, offer a promising path toward energy-efficient neural network computation. However, conventional quantization and compression techniques often…

Hardware Architecture · Computer Science 2025-12-23 Guan-Cheng Chen , Chieh-Lin Tsai , Pei-Hsuan Tsai , Yuan-Hao Chang

Error mitigation will play an important role in practical applications of near-term noisy quantum computers. Current error mitigation methods typically concentrate on correction quality at the expense of frugality (as measured by the number…

Quantum Physics · Physics 2025-05-08 Piotr Czarnik , Michael McKerns , Andrew T. Sornborger , Lukasz Cincio
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