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Modern transformer-based Large Language Models (LLMs) are constructed with a series of decoder blocks. Each block comprises three key components: (1) QKV generation, (2) multi-head attention, and (3) feed-forward networks. In batched…

Hardware Architecture · Computer Science 2024-06-21 Guseul Heo , Sangyeop Lee , Jaehong Cho , Hyunmin Choi , Sanghyeon Lee , Hyungkyu Ham , Gwangsun Kim , Divya Mahajan , Jongse Park

Transformers, while revolutionary, face challenges due to their demanding computational cost and large data movement. To address this, we propose HyFlexPIM, a novel mixed-signal processing-in-memory (PIM) accelerator for inference that…

Hardware Architecture · Computer Science 2025-06-03 Chang Eun Song , Priyansh Bhatnagar , Zihan Xia , Nam Sung Kim , Tajana Rosing , Mingu Kang

The proliferation of large language models (LLMs) is accelerating the integration of multimodal assistants into edge devices, where inference is executed under stringent latency and energy constraints, often exacerbated by intermittent…

Hardware Architecture · Computer Science 2026-01-29 Yanru Chen , Runyang Tian , Yue Pan , Zheyu Li , Weihong Xu , Tajana Rosing

Genome sequence alignment is the core of many biological applications. The advancement of sequencing technologies produces a tremendous amount of data, making sequence alignment a critical bottleneck in bioinformatics analysis. The existing…

Hardware Architecture · Computer Science 2023-01-26 Weihong Xu , Saransh Gupta , Niema Moshiri , Tajana Rosing

Large language models (LLMs) are widely used for natural language understanding and text generation. An LLM model relies on a time-consuming step called LLM decoding to generate output tokens. Several prior works focus on improving the…

Hardware Architecture · Computer Science 2025-02-28 Yintao He , Haiyu Mao , Christina Giannoula , Mohammad Sadrosadati , Juan Gómez-Luna , Huawei Li , Xiaowei Li , Ying Wang , Onur Mutlu

Processing-in-Memory (PIM) architectures offer a promising solution to the memory bottlenecks in data-intensive machine learning, yet often overlook the growing challenge of activation memory footprint. Conventional PIM approaches struggle…

Hardware Architecture · Computer Science 2026-04-21 Kosuke Matsushima , Yasuyuki Okoshi , Masato Motomura , Daichi Fujiki

Hyperdimensional computing (HDC) is an emerging computing paradigm that represents, manipulates, and communicates data using very long random vectors (aka hypervectors). Among different hardware platforms capable of executing HDC…

Hardware Architecture · Computer Science 2022-05-24 Robert Guirado , Abbas Rahimi , Geethan Karunaratne , Eduard Alarcón , Abu Sebastian , Sergi Abadal

The speed of modern digital systems is severely limited by memory latency (the ``Memory Wall'' problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic--In--Memory (LiM)…

Hardware Architecture · Computer Science 2023-04-14 Fabrizio Ottati , Giovanna Turvani , Marco Vacca , Guido Masera

Our ISCA 2015 paper provides a new programmable processing-in-memory (PIM) architecture and system design that can accelerate key data-intensive applications, with a focus on graph processing workloads. Our major idea was to completely…

Hardware Architecture · Computer Science 2023-06-28 Junwhan Ahn , Sungpack Hong , Sungjoo Yoo , Onur Mutlu , Kiyoung Choi

All-pairs shortest paths (APSP) remains a major bottleneck for large-scale graph analytics, as data movement with cubic complexity overwhelms the bandwidth of conventional memory hierarchies. In this work, we propose RAPID-Graph to address…

Hardware Architecture · Computer Science 2026-01-29 Yanru Chen , Zheyu Li , Keming Fan , Runyang Tian , John Hsu , Weihong Xu , Minxuan Zhou , Tajana Rosing

We introduce IMPACT, a set of high-throughput main memory-based timing attacks that leverage characteristics of processing-in-memory (PiM) architectures to establish covert and side channels. IMPACT enables high-throughput communication and…

Deep neural networks with large model sizes achieve state-of-the-art results for tasks in computer vision (CV) and natural language processing (NLP). However, these large-scale models are too compute- or memory-intensive for…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-10-29 Yang Hu , Connor Imes , Xuanang Zhao , Souvik Kundu , Peter A. Beerel , Stephen P. Crago , John Paul N. Walters

This paper evaluates the efficacy of recent commercial processing-in-memory (PIM) solutions to accelerate fast Fourier transform (FFT), an important primitive across several domains. Specifically, we observe that efficient implementations…

Hardware Architecture · Computer Science 2023-08-09 Mohamed Assem Ibrahim , Shaizeen Aga

Analog compute-in-memory (CIM) in static random-access memory (SRAM) is promising for accelerating deep learning inference by circumventing the memory wall and exploiting ultra-efficient analog low-precision arithmetic. Latest analog CIM…

Hardware Architecture · Computer Science 2024-07-19 Zhiyu Chen , Ziyuan Wen , Weier Wan , Akhil Reddy Pakala , Yiwei Zou , Wei-Chen Wei , Zengyi Li , Yubei Chen , Kaiyuan Yang

While scaling laws have been continuously validated in large language models (LLMs) with increasing model parameters, the inherent tension between the inference demands of LLMs and the limited resources of edge devices poses a critical…

Processing In Memory (PIM) accelerators are promising architecture that can provide massive parallelization and high efficiency in various applications. Such architectures can instantaneously provide ultra-fast operation over extensive…

Hardware Architecture · Computer Science 2022-07-26 Kazi Abu Zubair , Sumit Kumar Jha , David Mohaisen , Clayton Hughes , Amro Awad

Increasing AI computing demands and slowing transistor scaling have led to the advent of Multi-Chip-Module (MCMs) based accelerators. MCMs enable cost-effective scalability, higher yield, and modular reuse by partitioning large chips into…

Hardware Architecture · Computer Science 2025-05-06 Ritik Raj , Shengjie Lin , William Won , Tushar Krishna

The use of hybrid scheme combining the message passing programming models for inter-node parallelism and the shared memory programming models for node-level parallelism is widely spread. Existing extensive practices on hybrid Message…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-07-23 Huan Zhou , Jose Gracia , Naweiluo Zhou , Ralf Schneider

Processing-in-DRAM (DRAM-PIM) has emerged as a promising technology for accelerating memory-intensive operations in modern applications, such as Large Language Models (LLMs). Despite its potential, current software stacks for DRAM-PIM face…

Hardware Architecture · Computer Science 2025-06-03 Yongwon Shin , Dookyung Kang , Hyojin Sung

In the exascale computing era, optimizing MPI collective performance in high-performance computing (HPC) applications is critical. Current algorithms face performance degradation due to system call overhead, page faults, or data-copy…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-05-19 Jiajun Huang , Kaiming Ouyang , Yujia Zhai , Jinyang Liu , Min Si , Ken Raffenetti , Hui Zhou , Atsushi Hori , Zizhong Chen , Yanfei Guo , Rajeev Thakur