Related papers: A Hierarchical Dataflow-Driven Heterogeneous Archi…
The increasing use of heterogeneous embedded systems with multi-core CPUs and Graphics Processing Units (GPUs) presents important challenges in effectively exploiting pipeline, task and data-level parallelism to meet throughput requirements…
FPGA-based data processing in datacenters is increasing in popularity due to the demands of modern workloads and the ensuing necessity for specialization in hardware. Driven by this trend, vendors are rapidly adapting reconfigurable devices…
Today's increasing demand for wirelessly uploading a large volume of User Generated Content (UGC) is still significantly limited by the throttled backhaul of residential broadband (typically between 1 and 3Mbps). We propose BaPu, a…
The growing volume of data in modern applications has led to significant computational costs in conventional processor-centric systems. Processing-in-memory (PIM) architectures alleviate these costs by moving computation closer to memory,…
The attention layer, a core component of Transformer-based LLMs, brings out inefficiencies in current GPU systems due to its low operational intensity and the substantial memory requirements of KV caches. We propose a High-bandwidth…
The increase in the number of base station (BS) antennas calls for efficient solutions to deal with the increased interconnection bandwidth and processing complexity of traditional centralized approaches. Decentralized approaches are thus…
We are proposing fully parallel and maximally distributed hardware realization of a generic neuro-computing system. More specifically, the proposal relates to the wireless sensor networks technology to serve as a massively parallel and…
The Bulk Synchronous Parallel(BSP) computational model has emerged as the dominant distributed framework to build large-scale iterative graph processing systems. While its implementations(e.g., Pregel, Giraph, and Hama) achieve high…
Stream processing acceleration is driven by the continuously increasing volume and velocity of data generated on the Web and the limitations of storage, computation, and power consumption. Hardware solutions provide better performance and…
Transformer models serve as the backbone of many state-ofthe-art language models, and most use the scaled dot-product attention (SDPA) mechanism to capture relationships between tokens. However, the straightforward implementation of SDPA…
Deep neural network (DNN) hardware (HW) accelerators have achieved great success in improving DNNs' performance and efficiency. One key reason is dataflow in executing a DNN layer, including on-chip data partitioning, computation…
The next generations of wireless networks are envisioned to integrate communications, sensing, and computing into a unified platform, demanding ultra-high data rates, submillisecond latency, and unprecedented energy efficiency. However,…
Efficient management of heterogeneous traffic with varying priorities is critical in Wireless Body Area Networks (WBANs). The priority mechanisms embedded in Media Access Control (MAC) schemes largely govern the performance of WBAN in terms…
In this paper, we consider the problem of link scheduling in multi-hop wireless networks under general interference constraints. Our goal is to design scheduling schemes that do not use per-flow or per-destination information, maintain a…
The use of FPGAs for efficient graph processing has attracted significant interest. Recent memory subsystem upgrades including the introduction of HBM in FPGAs promise to further alleviate memory bottlenecks. However, modern multi-channel…
By allowing a large number of links to be simultaneously transmitted, directional antenna arrays with beamforming have been envisioned as a promising candidate to reach unprecedented levels of spatial isolation. To achieve the high…
Digital backpropagation (DBP) is one of the most effective techniques for compensating nonlinear distortions in coherent optical fiber communication systems. However, its practical application to wideband transmission remains limited by…
Page placement is a critical problem for memoryintensive applications running on a shared-memory multiprocessor with a non-uniform memory access (NUMA) architecture. State-of-the-art page placement mechanisms interleave pages evenly across…
Energy preservation is one of the most important challenges in wireless sensor networks. In most applications, sensor networks consist of hundreds or thousands nodes that are dispersed in a wide field. Hierarchical architectures and data…
In this paper, we propose TAPA, an end-to-end framework that compiles a C++ task-parallel dataflow program into a high-frequency FPGA accelerator. Compared to existing solutions, TAPA has two major advantages. First, TAPA provides a set of…