Related papers: A demonstrator for a real-time AI-FPGA-based trigg…
This paper presents a novel pixel chip readout scheme: the Region-of-Interest Readout Circuit (ROIRC), which is designed for large area, large array pixel chips and Gas Pixel Detector (GPD). This design employs a sentinel pixel detection…
The ATLAS experiment at the Large Hadron Collider employs a two-level trigger system to record data at an average rate of 1 kHz from physics collisions, starting from an initial bunch crossing rate of 40 MHz. During the LHC Run 2…
The upgrades of the Belle experiment and the KEKB accelerator aim to increase the data set of the experiment by the factor 50. This will be achieved by increasing the luminosity of the accelerator which requires a significant upgrade of the…
The PHENIX collaboration has measured low momentum direct photon radiation in Au+Au collisions at 200 GeV, 62.4 GeV and 39 GeV, in Cu+Cu at 200 GeV as well as in p+p, p+Au and d+Au at $\sqrt{s_{NN}} =$ 200 GeV. In these measurements PHENIX…
The ALICE Central Trigger Processor (CTP) is going to be upgraded for LHC Run 3 with completely new hardware and a new Trigger and Timing Control (TTC-PON) system based on a Passive Optical Network (PON) system. The new trigger system has…
Low-precision is the first order knob for achieving higher Artificial Intelligence Operations (AI-TOPS). However the algorithmic space for sub-8-bit precision compute is diverse, with disruptive changes happening frequently, making FPGAs a…
Contemporary field-programmable gate arrays (FPGAs) are predestined for the application of finite impulse response (FIR) filters. Their embedded digital signal processing (DSP) blocks for multiply-accumulate operations enable efficient…
The objective of this paper is to design and implement an intelligent Traffic Light Controller system for a four way road intersection. The design is carried out using Verilog, and the hardware is implemented on a FPGA. The chosen…
This paper presents a comprehensive review of recent advances in deploying convolutional neural networks (CNNs) for object detection, classification, and tracking on Field Programmable Gate Arrays (FPGAs). With the increasing demand for…
The J/$\psi$ yields in heavy ion collisions are expected to be a promising probe of deconfined matter, since theoretical models predict that the J/$\psi$ production could be strongly suppressed due to color screening effect in a Quark Gluon…
Throughout the history of the RHIC physics program, questions concerning the dynamics of heavy quarks have generated much experimental and theoretical investigation. A major focus of the PHENIX experiment is the measurement of these quarks…
A testbeam telescope, based on ATLAS IBL silicon pixel modules, has been built. It comprises six planes of planar silicon sensors with 250 x 50 um^2 pitch, read out by ATLAS FE-I4 chips. In the CERN SPS H8 beamline (180 GeV pi+) a…
This paper proposes an adaptive admittance controller for improving efficiency and safety in physical human-robot interaction (pHRI) tasks in small-batch manufacturing that involve contact with stiff environments, such as drilling,…
A full replacement of the existing muon trigger system in the CMS (Compact Muon Solenoid) detector is planned for operating at the maximum instantaneous luminosities of about $5-7.5\times10^{34}$ cm$^{-2}$ s$^{-1}$ expected in HL-LHC (High…
Direct photons are ideal tools to investigate kinematical and thermodynamical conditions of heavy ion collisions since they are emitted from all stages of the collision and once produced they leave the interaction region without further…
Artificial intelligence (AI) is increasingly deployed in real-time and energy-constrained environments, driving demand for hardware platforms that can deliver high performance and power efficiency. While central processing units (CPUs) and…
Digital off-detector electronics in trigger and data acquisition systems of High-Energy Physics experiments is often implemented by means of SRAM-based FPGAs, which make it possible to achieve reconfigurable, real-time processing and…
In this paper, we propose an architecture for FPGA emulation of mixed-signal systems that achieves high accuracy at a high throughput. We represent the analog output of a block as a superposition of step responses to changes in its analog…
We present a method for the evaluation, at the first level of trigger, of logical conditions with high time resolution, using the digitized times of fast signals delivered in the detectors of high rate experiments. We describe a…
A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is…