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The Compute Express Link (CXL) technology facilitates the extension of CPU memory through byte-addressable SerDes links and cascaded switches, creating complex heterogeneous memory systems where CPU access to various endpoints differs in…

Hardware Architecture · Computer Science 2025-11-06 Yiqi Chen , Xiping Dong , Zhe Zhou , Zhao Wang , Jie Zhang , Guangyu Sun

Memory dominates datacenter system cost and power. Memory expansion via Compute Express Link (CXL) is an effective way to provide additional memory at lower cost and power, but its effective use requires software-level tiering for…

Increasing workload demands and emerging technologies necessitate the use of various memory and storage tiers in computing systems. This paper presents results from a CXL-based Experimental Memory Request Logger that reveals precise memory…

Operating Systems · Computer Science 2025-08-14 Vinicius Petrucci , Felippe Zacarias , David Roberts

Transaction processing systems are the crux for modern data-center applications, yet current multi-node systems are slow due to network overheads. This paper advocates for Compute Express Link (CXL) as a network alternative, which enables…

Hardware Architecture · Computer Science 2025-07-24 Zhao Wang , Yiqi Chen , Cong Li , Dimin Niu , Tianchan Guan , Zhaoyang Du , Xingda Wei , Guangyu Sun

The Compute Express Link (CXL) interconnect makes it feasible to integrate diverse types of memory into servers via its byte-addressable SerDes links. Considering the various access latency, harnessing the full potential of CXL-based…

Hardware Architecture · Computer Science 2024-09-12 Zhe Zhou , Yiqi Chen , Tao Zhang , Yang Wang , Ran Shu , Shuotao Xu , Peng Cheng , Lei Qu , Yongqiang Xiong , Jie Zhang , Guangyu Sun

Memory tiering provides a cost-effective solution to increase memory capacity, utilization, and even bandwidth. Memory tiering relies on system software for memory profiling, detection of frequently accessed pages, and page migration. Such…

Operating Systems · Computer Science 2026-04-15 Xi Wang , Jie Liu , Shuangyan Yang , Jongryool Kim , Pengfei Su , Dong Li

Recent Serverless workloads tend to be largescaled/CPU-memory intensive, such as DL, graph applications, that require dynamic memory-to-compute resources provisioning. Meanwhile, recent solutions seek to design page management strategies…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-09-26 Yuze Li , Shunyu Yao

Memory disaggregation is an emerging technology that decouples memory from traditional memory buses, enabling independent scaling of compute and memory. Compute Express Link (CXL), an open-standard interconnect technology, facilitates…

Hardware Architecture · Computer Science 2025-03-27 Yujie Yang , Lingfeng Xiang , Peiran Du , Zhen Lin , Weishu Deng , Ren Wang , Andrey Kudryavtsev , Louis Ko , Hui Lu , Jia Rao

Interconnection is crucial for computing systems. However, the current interconnection performance between processors and devices, such as memory devices and accelerators, significantly lags behind their computing performance, severely…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-02-21 Chen Chen , Xinkui Zhao , Guanjie Cheng , Yuesheng Xu , Shuiguang Deng , Jianwei Yin

As modern LLMs support thousands to millions of tokens, KV caches grow to hundreds of gigabytes, stressing memory capacity and bandwidth. Existing solutions, such as KV cache pruning and offloading, alleviate these but underutilize hardware…

Performance · Computer Science 2026-04-21 Mao Lin , Xi Wang , Guilherme Cox , Dong Li , Hyeran Jeon

Compute eXpress Link (CXL) is emerging as a promising memory interface technology. However, its performance characteristics remain largely unclear due to the limited availability of production hardware. Key questions include: What are the…

Performance · Computer Science 2025-10-14 Xi Wang , Jie Liu , Jianbo Wu , Shuangyan Yang , Jie Ren , Bhanu Shankar , Dong Li

The proliferation of data-intensive applications, ranging from large language models to key-value stores, increasingly stresses memory systems with mixed read-write access patterns. Traditional half-duplex architectures such as DDR5 are…

Operating Systems · Computer Science 2025-08-25 Yiwei Yang , Yusheng Zheng , Yiqi Chen , Zheng Liang , Kexin Chu , Zhe Zhou , Andi Quinn , Wei Zhang

Compute Express Link (CXL) is a rapidly emerging coherent interconnect standard that provides opportunities for memory pooling and sharing. Memory sharing is a well-established software feature that improves memory utilization by avoiding…

Emerging Technologies · Computer Science 2024-04-05 Sunita Jain , Nagaradhesh Yeleswarapu , Hasan Al Maruf , Rita Gupta

The growing prevalence of data-intensive workloads, such as artificial intelligence (AI), machine learning (ML), high-performance computing (HPC), in-memory databases, and real-time analytics, has exposed limitations in conventional memory…

In our exploration of Composable Memory systems utilizing CXL, we focus on overcoming adoption barriers at Hyperscale, underscored by economic models demonstrating Total Cost of Ownership (TCO). While CXL addresses the pressing memory…

Emerging Technologies · Computer Science 2024-04-05 Angelos Arelakis , Nilesh Shah , Yiannis Nikolakopoulos , Dimitrios Palyvos-Giannas

Indexes are critical for efficient data retrieval and updates in modern databases. Recent advances in machine learning have led to the development of learned indexes, which model the cumulative distribution function of data to predict…

Databases · Computer Science 2026-04-27 Xinyi Zhang , Liang Liang , Anastasia Ailamaki , Jianliang Xu

Memory tiering systems seek cost-effective memory scaling by adding multiple tiers of memory. For maximum performance, frequently accessed (hot) data must be placed close to the host in faster tiers and infrequently accessed (cold) data can…

Operating Systems · Computer Science 2025-08-07 Sujay Yadalam , Konstantinos Kanellis , Michael Swift , Shivaram Venkataraman

Hybrid main memory systems combine both performance and capacity advantages from heterogeneous memory technologies. With larger capacities, higher associativities, and finer granularities, hybrid memory systems currently exhibit significant…

Hardware Architecture · Computer Science 2024-08-27 Yiwei Li , Boyu Tian , Mingyu Gao

Although every individual invented storage technology made a big step towards perfection, none of them is spotless. Different data store essentials such as performance, availability, and recovery requirements have not met together in a…

Hardware Architecture · Computer Science 2019-04-29 Morteza Hoseinzadeh

A heterogeneous memory has a single address space with fast access to some addresses (a fast tier of DRAM) and slow access to other addresses (a capacity tier of CXL-attached memory or NVM). A tiered memory system aims to maximize the…

Emerging Technologies · Computer Science 2025-10-28 Rohan Kadekodi , Haoran Peng , Gilbert Bernstein , Michael D. Ernst , Baris Kasikci
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