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Matrix factorization (MF) discovers latent features from observations, which has shown great promises in the fields of collaborative filtering, data compression, feature extraction, word embedding, etc. While many problem-specific…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-08-14 Wei Tan , Shiyu Chang , Liana Fong , Cheng Li , Zijun Wang , Liangliang Cao

This paper addresses the problem of adding redundancy to a collection of physical objects so that the overall system is more robust to failures. In contrast to its information counterpart, which can exploit parity to protect multiple…

Information Theory · Computer Science 2017-11-09 Jennifer Tang , Da Wang , Yury Polyanskiy , Gregory Wornell

Reliability-based design optimization (RBDO) provides a rational and sound framework for finding the optimal design while taking uncertainties into ac-count. The main issue in implementing RBDO methods, particularly stochastic simu-lation…

Applications · Statistics 2020-03-03 Wang-Sheng Liu , Sai Hung Cheung

In large-scale LLM pre-training systems with 100k+ GPUs, failures become the norm rather than the exception, and restart costs can dominate wall-clock training time. However, existing fault-tolerance mechanisms are largely unprepared for…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-29 Jin Lee , Zhonghao Chen , Xuhang He , Robert Underwood , Bogdan Nicolae , Franck Cappello , Xiaoyi Lu , Sheng Di , Zheng Zhang

We propose a novel technique for optimizing a modular fault-tolerant quantum computing architecture, taking into account any desired space-time trade-offs between the number of physical qubits and the fault-tolerant execution time of a…

Supercomputing systems today often come in the form of large numbers of commodity systems linked together into a computing cluster. These systems, like any distributed system, can have large numbers of independent hardware components…

Distributed, Parallel, and Cluster Computing · Computer Science 2007-05-23 Michael Treaster

A low-latency and energy-efficient tensor algebra accelerator design must optimize how data movement and operations are scheduled (i.e., mapped) in the accelerator architecture. A key mapping optimization is fusion, meaning holding data…

Hardware Architecture · Computer Science 2026-05-05 Tanner Andrulis , Michael Gilbert , Vivienne Sze , Joel S. Emer

In modern low-power embedded platforms, floating-point (FP) operations emerge as a major contributor to the energy consumption of compute-intensive applications with large dynamic range. Experimental evidence shows that 50% of the energy…

Hardware Architecture · Computer Science 2017-11-29 Giuseppe Tagliavini , Stefan Mach , Davide Rossi , Andrea Marongiu , Luca Benini

With rapid integration of power sources with uncertainty, robustness must be carefully considered in the transmission constrained unit commitment (TCUC) problem. The overall computational complexity of the robust TCUC methods is closely…

Optimization and Control · Mathematics 2018-10-16 Xuan Li , Qiaozhu Zhai , Xiaohong Guan

While physics-based computing can offer speed and energy efficiency compared to digital computing, it also is subject to errors that must be mitigated. For example, many error mitigation methods have been proposed for quantum computing.…

Emerging Technologies · Computer Science 2024-01-30 Maxwell Aifer , Denis Melanson , Kaelan Donatella , Gavin Crooks , Thomas Ahle , Patrick J. Coles

Reliability has taken centre stage in the development of high-performance computing processors. A Surge of interest is noticeable in recent times in formulating fault and failure models, understanding failure mechanism and strategizing…

Hardware Architecture · Computer Science 2022-03-16 Shashikiran Venkatesha , Ranjani Parthasarathi

In modern computing units, division operations are generally slower than other arithmetic operations and require more resources, such as area and power, than multiplication. To reduce the delay, fast division algorithms use an initial…

Traditional heterogeneous parallel algorithms, designed for heterogeneous clusters of workstations, are based on the assumption that the absolute speed of the processors does not depend on the size of the computational task. This assumption…

Distributed, Parallel, and Cluster Computing · Computer Science 2011-09-15 Alexey Lastovetsky , Ravi Reddy , Vladimir Rychkov , David Clarke

Due to their growing popularity and computational cost, deep neural networks (DNNs) are being targeted for hardware acceleration. A popular architecture for DNN acceleration, adopted by the Google Tensor Processing Unit (TPU), utilizes a…

Machine Learning · Computer Science 2018-02-20 Jeff Zhang , Tianyu Gu , Kanad Basu , Siddharth Garg

Reliability has emerged as a key topic of interest for researchers around the world to detect and/or mitigate the side effects of decreasing transistor sizes, such as soft errors. Traditional solutions, like DMR and TMR, incur significant…

Hardware Architecture · Computer Science 2019-10-22 Bharath Srinivas Prabakaran , Mihika Dave , Florian Kriebel , Semeen Rehman , Muhammad Shafique

Metal additive manufacturing (AM) processes often fabricate a near-net shape that includes the as-designed part as well as the sacrificial support structures that need to be machined away by subtractive manufacturing (SM), for instance…

Computational Engineering, Finance, and Science · Computer Science 2021-08-09 Amir M. Mirzendehdel , Morad Behandish , Saigopal Nelaturi

Adaptive mesh refinement (AMR) is a classical technique about local refinement in space where needed, thus effectively reducing computational costs for HPC-based physics simulations. Although AMR has been used for many years, little…

Fluid Dynamics · Physics 2024-05-14 Dewen Liu , Shuai He , Haoran Cheng , Yadong Zeng

Approximate computing is an emerging paradigm where design accuracy can be traded off for benefits in design metrics such as design area, power consumption or circuit complexity. In this work, we present a novel paradigm to synthesize…

Hardware Architecture · Computer Science 2018-05-17 Soheil Hashemi , Hokchhay Tann , Sherief Reda

While recent advances in AI SoC design have focused heavily on accelerating tensor computation, the equally critical task of tensor manipulation, centered on high,volume data movement with minimal computation, remains underexplored. This…

Hardware Architecture · Computer Science 2025-06-18 Weiyu Zhou , Zheng Wang , Chao Chen , Yike Li , Yongkui Yang , Zhuoyu Wu , Anupam Chattopadhyay

The rapid updates in error-resilient applications along with their quest for high throughput have motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies that proposed imprecise functional…

Hardware Architecture · Computer Science 2022-06-29 Zahra Ebrahimi , Muhammad Zaid , Mark Wijtvliet , Akash Kumar
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