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RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in other physically nearby DRAM rows. RowHammer solutions perform preventive actions (e.g.,…

Aggressive memory density scaling causes modern DRAM devices to suffer from RowHammer, a phenomenon where rapidly activating a DRAM row can cause bit-flips in physically-nearby rows. Recent studies demonstrate that modern DRAM chips,…

RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of DRAM cells (DRAM row) induces bitflips in physically nearby DRAM rows (victim rows). To ensure robust DRAM operation, state-of-the-art…

RowHammer vulnerabilities pose a significant threat to modern DRAM-based systems, where rapid activation of DRAM rows can induce bit-flips in neighboring rows. To mitigate this, state-of-the-art host-side RowHammer mitigations typically…

Cryptography and Security · Computer Science 2025-05-16 Jeonghyun Woo , Prashant J. Nair

This paper provides the fundamental mechanisms of two types of row activation-induced bit flips and proposes in-DRAM protection techniques. RowBleed occurs when a victim row experiences charge leakage due to transistor's threshold voltage…

Cryptography and Security · Computer Science 2025-06-17 Seungki Hong , Dongha Kim , Jaehyung Lee , Reum Oh , Changsik Yoo , Sangjoon Hwang , Jooyoung Lee

We propose a new RowHammer mitigation mechanism, CoMeT, that prevents RowHammer bitflips with low area, performance, and energy costs in DRAM-based systems at very low RowHammer thresholds. The key idea of CoMeT is to use low-cost and…

As DRAM density increases, Rowhammer becomes more severe due to heightened charge leakage, reducing the number of activations needed to induce bit flips. The DDR5 standard addresses this threat with in-DRAM per-row activation counters…

Hardware Architecture · Computer Science 2025-07-25 Ravan Nazaraliyev , Saber Ganjisaffar , Nurlan Nazaraliyev , Nael Abu-Ghazaleh

We 1) present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per Row Activation Counting (PRAC) and 2) propose Chronus, a new mechanism that…

The Rowhammer vulnerability poses an increasing challenge with newer generations of DRAM and aggressive technology scaling. Existing mitigation techniques, such as Graphene, Twice, and Hydra, primarily rely on tracking activation counts for…

Cryptography and Security · Computer Science 2026-04-28 Lavi Jain , Venkata Kalyan Tavva

This paper focuses on mitigating DRAM Rowhammer attacks. In recent years, solutions like TRR have been deployed in DDR4 DRAM to track aggressor rows and then issue a mitigative action by refreshing neighboring victim rows. Unfortunately,…

Cryptography and Security · Computer Science 2024-04-26 Aamer Jaleel , Stephen W. Keckler , Gururaj Saileshwar

In order to shed more light on how RowHammer affects modern and future devices at the circuit-level, we first present an experimental characterization of RowHammer on 1580 DRAM chips (408x DDR3, 652x DDR4, and 520x LPDDR4) from 300 DRAM…

Hardware Architecture · Computer Science 2020-06-01 Jeremie S. Kim , Minesh Patel , A. Giray Yaglikci , Hasan Hassan , Roknoddin Azizi , Lois Orosa , Onur Mutlu

As DRAM scaling exacerbates RowHammer, DDR5 introduces per-row activation counting (PRAC) to track aggressor activity. However, PRAC indiscriminately increments counters on every activation -- including benign refreshes -- while relying…

Cryptography and Security · Computer Science 2026-04-23 Jumin Kim , Seungmin Baek , Hwayong Nam , Minbok Wi , Nam Sung Kim , Jung Ho Ahn

RowHammer attacks are a growing security and reliability concern for DRAMs and computer systems as they can induce many bit errors that overwhelm error detection and correction capabilities. System-level solutions are needed as process…

Hardware Architecture · Computer Science 2023-10-26 Steven C. Woo , Wendy Elsasser , Mike Hamburg , Eric Linstadt , Michael R. Miller , Taeksang Song , James Tringali

JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations using per-row activation counts. While recent PRAC implementations enable holistic mitigation…

Cryptography and Security · Computer Science 2025-06-16 Chris S. Lin , Jeonghyun Woo , Prashant J. Nair , Gururaj Saileshwar

The security vulnerabilities due to Rowhammer have worsened over the last decade, with existing in-DRAM solutions, such as TRR, getting broken with simple patterns. In response, the DDR5 specifications have been extended to support Per-Row…

Cryptography and Security · Computer Science 2024-07-16 Moinuddin Qureshi , Salman Qazi

JEDEC has introduced the Per Row Activation Counting (PRAC) framework for DDR5 and future DRAMs to enable precise counting of DRAM row activations. PRAC enables a holistic mitigation of Rowhammer attacks even at ultra-low Rowhammer…

Cryptography and Security · Computer Science 2025-05-16 Jeonghyun Woo , Chris S. Lin , Prashant J. Nair , Aamer Jaleel , Gururaj Saileshwar

Per Row Activation Counting (PRAC) has emerged as a robust framework for mitigating RowHammer (RH) vulnerabilities in modern DRAM systems. However, we uncover a critical vulnerability: a timing channel introduced by the Alert Back-Off (ABO)…

Cryptography and Security · Computer Science 2025-05-20 Jeonghyun Woo , Joyce Qu , Gururaj Saileshwar , Prashant J. Nair

Modern systems mitigate Rowhammer using victim refresh, which refreshes the two neighbours of an aggressor row when it encounters a specified number of activations. Unfortunately, complex attack patterns like Half-Double break…

Cryptography and Security · Computer Science 2023-08-30 Anish Saxena , Saurav Mathur , Moinuddin Qureshi

The Rowhammer vulnerability continues to get worse, with the Rowhammer Threshold (TRH) reducing from 139K activations to 4.8K activations over the last decade. Typical Rowhammer mitigations rely on tracking aggressor rows. The number of…

Cryptography and Security · Computer Science 2023-11-08 Anish Saxena , Moinuddin Qureshi

DRAM is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent data loss. Refresh operations degrade system performance by interfering with memory accesses. As DRAM chip density increases with…

Hardware Architecture · Computer Science 2022-09-22 Abdullah Giray Yağlıkçı , Ataberk Olgun , Minesh Patel , Haocong Luo , Hasan Hassan , Lois Orosa , Oğuz Ergin , Onur Mutlu
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