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The currently dominant AI/ML workloads, such as Large Language Models (LLMs), rely on the efficient execution of General Matrix-Matrix Multiplication (GEMM) operations. Thus, most systems are equipped with dedicated matrix hardware…

Hardware Architecture · Computer Science 2026-04-01 Luigi Altamura , Alessio Cicero , Mateo Vázquez Maceiras , Mohammad Ali Maleki , Pedro Trancoso

Convolutional neural network (CNN) inference on mobile devices demands efficient hardware acceleration of low-precision (INT8) general matrix multiplication (GEMM). The systolic array (SA) is a pipelined 2D array of processing elements…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-05-19 Zhi-Gang Liu , Paul N. Whatmough , Matthew Mattina

General matrix multiplication (GeMM) is a core operation in virtually all AI applications. Systolic array (SA) based architectures have shown great promise as GeMM hardware accelerators thanks to their speed and energy efficiency.…

Hardware Architecture · Computer Science 2025-01-13 Md Mizanur Rahaman Nayan , Ritik Raj , Gouse Basha Shaik , Tushar Krishna , Azad J Naeemi

Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs), designed…

Hardware Architecture · Computer Science 2026-03-24 Pragun Jaswal , L. Hemanth Krishna , B. Srinivasu

Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data movements. Even…

Hardware Architecture · Computer Science 2023-09-11 C. Peltekis , D. Filippas , G. Dimitrakopoulos , C. Nicopoulos

The acceleration of deep-learning kernels in hardware relies on matrix multiplications that are executed efficiently on Systolic Arrays (SA). To effectively trade off deep-learning training/inference quality with hardware cost, SA…

Hardware Architecture · Computer Science 2023-09-11 D. Filippas , C. Peltekis , G. Dimitrakopoulos , C. Nicopoulos

The computation and memory-intensive nature of DNNs limits their use in many mobile and embedded contexts. Application-specific integrated circuit (ASIC) hardware accelerators employ matrix multiplication units (such as the systolic arrays)…

Hardware Architecture · Computer Science 2024-02-02 Ruiqi Sun , Yinchen Ni , Xin He , Jie Zhao , An Zou

There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements (PEs) interacting via custom buffer hierarchies and networks-on-chip. The…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-06-22 Gordon E. Moon , Hyoukjun Kwon , Geonhwa Jeong , Prasanth Chatarasi , Sivasankaran Rajamanickam , Tushar Krishna

General Matrix Multiplication (GEMM) is the cornerstone of HPC workloads and Deep Learning. State-of-the-art vendor libraries tune tensor layouts, parallelization schemes, and cache blocking to minimize data movement across the memory…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-04-09 Evangelos Georganas , Alexander Heinecke , Pradeep Dubey

Massive MIMO is a cornerstone of next-generation wireless communication, offering significant gains in capacity, reliability, and energy efficiency. However, to meet emerging demands such as high-frequency operation, wide bandwidths,…

Signal Processing · Electrical Eng. & Systems 2026-01-21 Ali Rasteh , Andrew Hennessee , Ishaan Shivhare , Siddharth Garg , Sundeep Rangan , Brandon Reagen

The GEneral Matrix Multiplication (GEMM) is one of the essential algorithms in scientific computing. Single-thread GEMM implementations are well-optimised with techniques like blocking and autotuning. However, due to the complexity of…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-01-15 Yufan Xia , Marco De La Pierre , Amanda S. Barnard , Giuseppe Maria Junior Barca

Convolutional neural network (CNN) inference on mobile devices demands efficient hardware acceleration of low-precision (INT8) general matrix multiplication (GEMM). Exploiting data sparsity is a common approach to further accelerate GEMM…

Hardware Architecture · Computer Science 2020-10-14 Zhi-Gang Liu , Paul N. Whatmough , Matthew Mattina

Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the…

With increasing diversity in Deep Neural Network(DNN) models in terms of layer shapes and sizes, the research community has been investigating flexible/reconfigurable accelerator substrates. This line of research has opened up two…

Hardware Architecture · Computer Science 2022-04-26 Ananda Samajdar , Michael Pellauer , Tushar Krishna

Transformers have revolutionized deep learning with applications in natural language processing, computer vision, and beyond. However, their computational demands make it challenging to deploy them on low-power edge devices. This paper…

Hardware Architecture · Computer Science 2025-07-18 Rohit Prasad

The paper discusses how Systolic Arrays can improve matrix multiplication for deep neural networks (DNNs). With AI models like OpenAI's GPT now containing trillions of parameters, the need for efficient matrix multiplication is more…

Hardware Architecture · Computer Science 2024-10-31 Tejas Raja

General Matrix Multiplication (GEMM) is a critical kernel in high-performance computing and deep learning. While modern architectures like ARM's Scalable Matrix Extension (SME) introduce dedicated hardware for matrix operations, existing…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-12-29 Chencheng Deng , Weiling Yang , Jianbin Fang , Dezun Dong

General Matrix Multiplication (GEMM) is a fundamental operation in many scientific workloads, signal processing, and particularly deep learning. It is often a bottleneck for performance and energy efficiency, especially in edge environments…

Hardware Architecture · Computer Science 2025-11-11 Ilias Papalamprou , Dimosthenis Masouros , Ioannis Loudaros , Francky Catthoor , Dimitrios Soudris

In order to follow the ever-growing computational complexity and data intensity of state-of-the-art AI models, new computing paradigms are being proposed. These paradigms aim at achieving high energy efficiency by mitigating the Von Neumann…

Artificial Intelligence · Computer Science 2025-08-01 Cristian Sestito , Shady Agwa , Themis Prodromakis

Many scientific computing problems can be reduced to Matrix-Matrix Multiplications (MMM), making the General Matrix Multiply (GEMM) kernels in the Basic Linear Algebra Subroutine (BLAS) of interest to the high-performance computing…

Hardware Architecture · Computer Science 2023-05-31 Louis Ledoux , Marc Casas
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