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In this work, we propose a configurable many-core overlay for high-performance embedded computing. The size of internal memory, supported operations and number of ports can be configured independently for each core of the overlay. The…
We present a Time-to-Digital Converter (TDC) implemented on a 16 nm Xilinx UltraScale Plus FPGA that achieves a resolution of 1.15 ps, RMS precision of 3.38 ps, a differential nonlinearity (DNL) of [-0.43, 0.24] LSB, and an integral…
The efficient decomposition of multi-controlled gates is a significant factor in quantum compiling, both in circuit depth and T-gate count. Recent work has demonstrated that qudits have the potential to reduce resource requirements from…
The surface code is a powerful quantum error correcting code that can be defined on a 2-D square lattice of qubits with only nearest neighbor interactions. Syndrome and data qubits form a checkerboard pattern. Information about errors is…
Rydberg atom arrays have recently emerged as one of the most promising platforms for quantum simulation and quantum information processing. However, as is the case for other experimental platforms, the longer-term success of the Rydberg…
To address the challenge posed by noise in real quantum devices, quantum error mitigation techniques play a crucial role. These techniques are resource-efficient, making them suitable for implementation in noisy intermediate-scale quantum…
Quantum error correction (QEC) is essential for quantum computers to perform useful algorithms, but large-scale fault-tolerant computation remains out of reach due to demanding requirements on operation fidelity and the number of…
Iterative methods on irregular grids have been used widely in all areas of comptational science and engineering for solving partial differential equations with complex geometry. They provide the flexibility to express complex shapes with…
Quantum error correction (QEC) underpins practical fault-tolerant quantum computing (FTQC) by addressing the fragility of quantum states and mitigating decoherence-induced errors. As quantum devices scale, integrating robust QEC protocols…
The construction of a quantum computer remains a fundamental scientific and technological challenge, in particular due to unavoidable noise. Quantum states and operations can be protected from errors using protocols for fault-tolerant…
Extreme edge platforms, such as in-vehicle smart devices, require efficient deployment of quantized deep neural networks (DNNs) to enable intelligent applications with limited amounts of energy, memory, and computing resources. However,…
Pseudorandom number generation (PRNG) is a key element in hardware security platforms like field-programmable gate array FPGA circuits. In this article, 18 PRNGs belonging in 4 families (xorshift, LFSR, TGFSR, and LCG) are physically…
Achieving scalable, fault-tolerant quantum computation requires quantum memory architectures that minimize error correction overhead while preserving coherence. This work presents a framework for high-dimensional qudit memory in…
As enterprises embrace blockchain technology, many real-world applications have been developed and deployed using permissioned blockchain platforms (access to network is controlled and given to only nodes with known identities). Such…
In this paper we study from a numerical analysis perspective the Fractional Step Kinetic Monte Carlo (FS-KMC) algorithms proposed in [1] for the parallel simulation of spatially distributed particle systems on a lattice. FS-KMC are…
Quantum bits have technological imperfections. Additionally, the capacity of a component that can be implemented feasibly is limited. Therefore, distributed quantum computation is required to scale up quantum computers. This dissertation…
We describe a scheme for quantum error correction that employs feedback and weak measurement rather than the standard tools of projective measurement and fast controlled unitary gates. The advantage of this scheme over previous protocols…
Nowadays, locating software components responsible for observed failures is one of the most expensive and error-prone tasks in the software development process. To improve the debugging process efficiency, some effort was already made to…
Programmable Logic Devices (PLDs) continue to grow in size and currently contain several millions of gates. At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can…
Convolutional Neural Networks (CNNs) are widely used in deep learning applications, e.g. visual systems, robotics etc. However, existing software solutions are not efficient. Therefore, many hardware accelerators have been proposed…