Related papers: A Novel Fault-Tolerant Logic Style with Self-Check…
Quantum error correction (QEC) is considered a deciding component in enabling practical quantum computing. Stabilizer codes, and in particular topological surface codes, are promising candidates for implementing QEC by redundantly encoding…
Test response compaction for integrated circuits (ICs) with scan-based design-for-testability (DFT) support in the presence of unknown logic values (Xs) is investigated from a combinatorial viewpoint. The theoretical foundations of X-codes,…
In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for…
The decoherence effect caused by the coupling between the system and the environment undoubtedly leads to the errors in efficient implementations of two (or three) qubit logical gates in quantum information processing. Fortunately,…
As the size and complexity of a quantum computer increases, quantum bit (qubit) characterization and gate optimization become complex and time-consuming tasks. Current calibration techniques require complicated and verbose measurements to…
In this short review, I draw attention to new developments in the theory of fault tolerance in quantum computation that may give concrete direction to future work in the development of superconducting qubit systems. The basics of quantum…
All-optical integrated circuits for computing and information processing have been pursued for decades as a potential strategy to overcome the speed limitations intrinsic to electronics. However feasible on-chip integrated logic units and…
Chip designers outsource chip fabrication to external foundries, but at the risk of IP theft. Logic locking, a promising solution to mitigate this threat, adds extra logic gates (key gates) and inputs (key bits) to the chip so that it…
Fault-tolerant quantum computation allows quantum computations to be carried out while resisting unwanted noise. Several error-correcting codes have been developed to achieve this task, but none alone are capable of universal quantum…
It is an oft-cited fact that no quantum code can support a set of fault-tolerant logical gates that is both universal and transversal. This no-go theorem is generally responsible for the interest in alternative universality constructions…
It is now widely accepted that the CMOS technology implementing irreversible logic will hit a scaling limit beyond 2016, and that the increased power dissipation is a major limiting factor. Reversible computing can potentially require…
Logic Locking is a well-accepted protection technique to enable trust in the outsourced design and fabrication processes of integrated circuits (ICs) where the original design is modified by incorporating additional key gates in the…
Recent proposals using heterostructures of superconducting and either topologically insulating or semiconducting layers have been put forth as possible platforms for topological quantum computation. These systems are predicted to contain…
Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL)…
Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection based on logic encryption (LE). Unlike established schemes…
Exploiting the effects of quantum interference we put forward an idea of designing three primary logic gates, OR, AND and NOT, using a benzene molecule. Under a specific molecule-lead interface geometry, anti-resonant states appear which…
The composite rotation approach has been used to develop a range of robust quantum logic gates, including single qubit gates and two qubit gates, which are resistant to systematic errors in their implementation. Single qubit gates based on…
This PhD dissertation investigates garbage-free reversible computing systems from abstract design to physical gate-level implementation. Designed in reversible logic, we propose a ripple-block carry adder and work towards a reversible…
We propose a novel hybrid single-electron device for reprogrammable low-power logic operations, the magnetic single-electron transistor (MSET). The device consists of an aluminium single-electron transistors with a GaMnAs magnetic…
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of power dissipation in low power VLSI systems. This paper presented an idea of using the power gating structure for reducing the sub threshold…