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Dynamic programming (DP) algorithms, such as All-Pairs Shortest Path (APSP) and genomic sequence alignment, are fundamental to many scientific domains but are severely bottlenecked by data movement on conventional architectures. While…

Hardware Architecture · Computer Science 2026-03-02 Tsung-Han Lu , Weihong Xu , Tajana Rosing

Modern computing systems suffer from the dichotomy between computation on one side, which is performed only in the processor (and accelerators), and data storage/movement on the other, which all other parts of the system are dedicated to.…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-05-14 Onur Mutlu , Saugata Ghose , Juan Gómez-Luna , Rachata Ausavarungnirun

PIM architectures aim to reduce data transfer costs between processors and memory by integrating processing units within memory layers. Prior PIM architectures have shown potential to improve energy efficiency and performance. However, such…

Hardware Architecture · Computer Science 2025-10-10 Parker Hao Tian , Zahra Yousefijamarani , Alaa Alameldeen

In this article, we introduce an instruction set architecture (ISA) for processing-in-memory (PIM) based deep neural network (DNN) accelerators. The proposed ISA is for DNN inference on PIM-based architectures. It is assumed that the…

Programming Languages · Computer Science 2023-08-15 Xiaoming Chen

Recently DRAM-based PIMs (processing-in-memories) with unmodified cell arrays have demonstrated impressive performance for accelerating AI applications. However, due to the very restrictive hardware constraints, PIM remains an accelerator…

Hardware Architecture · Computer Science 2023-10-17 Jaewoo Park , Sugil Lee , Jongeun Lee

As an emerging type of AI computing accelerator, SRAM Computing-In-Memory (CIM) accelerators feature high energy efficiency and throughput. However, various CIM designs and under-explored mapping strategies impede the full exploration of…

Hardware Architecture · Computer Science 2026-01-27 Jinwu Chen , Yuhui Shi , He Wang , Zhe Jiang , Jun Yang , Xin Si , Zhenhua Zhu

Processing-in-memory (PIM) has shown extraordinary potential in accelerating neural networks. To evaluate the performance of PIM accelerators, we present an ISA-based simulation framework including a dedicated ISA targeting neural networks…

Hardware Architecture · Computer Science 2024-02-29 Xinyu Wang , Xiaotian Sun , Yinhe Han , Xiaoming Chen

Processing-in-memory (PIM) architecture is an inherent match for data analytics application, but we observe major challenges to address when accelerating it using PIM. In this paper, we propose Darwin, a practical LRDIMM-based multi-level…

Systems and Control · Electrical Eng. & Systems 2025-09-23 Donghyuk Kim , Jae-Young Kim , Wontak Han , Jongsoon Won , Haerang Choi , Yongkee Kwon , Joo-Young Kim

Processing-in-memory architectures have been regarded as a promising solution for CNN acceleration. Existing PIM accelerator designs rely heavily on the experience of experts and require significant manual design overhead. Manual design…

Hardware Architecture · Computer Science 2024-02-29 Wanqian Li , Xiaotian Sun , Xinyu Wang , Lei Wang , Yinhe Han , Xiaoming Chen

With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms have evolved in two diverse directions -- one with ever-increasing connection density for better accuracy and the other with more compact sizing for energy…

Hardware Architecture · Computer Science 2021-07-07 Gokul Krishnan , Sumit K. Mandal , Chaitali Chakrabarti , Jae-sun Seo , Umit Y. Ogras , Yu Cao

While deep neural network (DNN)-based video denoising has demonstrated significant performance, deploying state-of-the-art models on edge devices remains challenging due to stringent real-time and energy efficiency requirements.…

Computer Vision and Pattern Recognition · Computer Science 2025-05-29 Shan Gao , Zhiqiang Wu , Yawen Niu , Xiaotao Li , Qingqing Xu

Due to amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become the bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and…

Hardware Architecture · Computer Science 2020-09-22 Kamil Khan , Sudeep Pasricha , Ryan Gary Kim

Spiking Neural Networks (SNNs) offer a promising alternative to Artificial Neural Networks (ANNs) for deep learning applications, particularly in resource-constrained systems. This is largely due to their inherent sparsity, influenced by…

Hardware Architecture · Computer Science 2023-10-27 Ilkin Aliyev. Kama Svoboda , Tosiron Adegbija

Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A…

Hardware Architecture · Computer Science 2023-04-04 Juan Gómez-Luna , Izzat El Hajj , Ivan Fernandez , Christina Giannoula , Geraldo F. Oliveira , Onur Mutlu

Co-exploration of neural architectures and hardware design is promising to simultaneously optimize network accuracy and hardware efficiency. However, state-of-the-art neural architecture search algorithms for the co-exploration are…

Neural and Evolutionary Computing · Computer Science 2020-03-24 Weiwen Jiang , Qiuwen Lou , Zheyu Yan , Lei Yang , Jingtong Hu , Xiaobo Sharon Hu , Yiyu Shi

3D die-stacked DRAM has emerged as a key technology for delivering high bandwidth and high density for applications such as high-performance computing, graphics, and machine learning. However, different applications place diverse and…

Hardware Architecture · Computer Science 2025-12-16 Victor Cai , Jennifer Zhou , Haebin Do , David Brooks , Gu-Yeon Wei

Large language model (LLM) decoding is a major inference bottleneck because its low arithmetic intensity makes performance highly sensitive to memory bandwidth. 3D-stacked near-memory processing (NMP) provides substantially higher local…

Hardware Architecture · Computer Science 2026-04-10 Chenyang Ai , Yixing Zhang , Haoran Wu , Yudong Pan , Lechuan Zhao , Wenhui OU

Processing-in-Memory (PIM) enhances memory with computational capabilities, potentially solving energy and latency issues associated with data transfer between memory and processors. However, managing concurrent computation and data flow…

Hardware Architecture · Computer Science 2025-05-09 Ahmed Mamdouh , Haoran Geng , Michael Niemier , Xiaobo Sharon Hu , Dayane Reis

Deep neural networks (DNNs) have been shown to outperform conventional machine learning algorithms across a wide range of applications, e.g., image recognition, object detection, robotics, and natural language processing. However, the high…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-04-23 Ye Yu , Yingmin Li , Shuai Che , Niraj K. Jha , Weifeng Zhang

With the recent growth in demand for large-scale deep neural networks, compute in-memory (CiM) has come up as a prominent solution to alleviate bandwidth and on-chip interconnect bottlenecks that constrain Von-Neuman architectures. However,…

Hardware Architecture · Computer Science 2024-03-19 Souvik Kundu , Anthony Sarah , Vinay Joshi , Om J Omer , Sreenivas Subramoney