Related papers: Novel Efficient Scalable QCA XOR and Full Adder De…

Quantum-dot cellular automata (QCA) is a likely candidate for future low power nano-scale electronic devices. Sequential circuits in QCA attract more attention due to its numerous application in digital industry. On the other hand,…

The present manuscript deals with the realization of Processing In-memory (PIM) computing architecture using Quantum Dot Cellular Automata (QCA) and Akers array. The PIM computing architecture becomes popular due to its effective framework…

In this work, we develop a method to use Quantum- Dot Cellular Automata (QCA) for universal quantum computing. This method is based conceptually on refocusing in NMR systems. We show how an array of QCA cells can be used for isolated single…

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272$\mu$W in 0.35$\mu$m technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for…

We have previously proposed a way of using coupled quantum dots to construct digital computing elements - quantum-dot cellular automata (QCA). Here we consider a different approach to using coupled quantum-dot cells in an architecture…

We present a new cellular data processing scheme, a hybrid of existing cellular automata (CA) and gate array architectures, which is optimized for realization at the quantum scale. For conventional computing, the CA-like external clocking…

This paper presents a novel architecture utilizing a 10T SRAM cell for XNOR-based in-memory computing, aimed at mitigating the extensive routing challenges typically encountered in conventional in-memory computing systems. By integrating a…

Quantum Approximation Optimization Algorithm (QAOA) is a highly advocated variational algorithm for solving the combinatorial optimization problem. One critical feature in the quantum circuit of QAOA algorithm is that it consists of…

In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate…

Variational quantum algorithms are believed to be promising for solving computationally hard problems and are often comprised of repeated layers of quantum gates. An example thereof is the quantum approximate optimization algorithm (QAOA),…

The Dadda algorithm is a parallel structured multiplier, which is quite faster as compared to array multipliers, i.e., Booth, Braun, Baugh-Wooley, etc. However, it consumes more power and needs a larger number of gates for hardware…

Near zero-energy computing describes the concept of executing logic operations below the (kBT ln 2) energy limit. Landauer discussed that it is impossible to break this limit as long as the computations are performed in the conventional,…

The quantum adder is an essential attribute of a quantum computer, just as classical adder is needed for operation of a digital computer. We model the quantum full adder as a realistic complex algorithm on a large number of qubits in an…

Quantum dot cellular automata (QCA) computing schemes use arrays of quantum dots as computational devices. Typically, these operate ideally by maintaining arrays in their ground state to ensure correct computational output. For large QCA…

Scaling the size of monolithic quantum computer systems is a difficult task. As the number of qubits within a device increases, a number of factors contribute to decreases in yield and performance. To meet this challenge, distributed…

Approximate multipliers are widely being advocated for energy-efficient computing in applications that exhibit an inherent tolerance to inaccuracy. However, the inclusion of accuracy as a key design parameter, besides the performance, area…

In this research, we create a scalable version of the quantum Fourier transform-based arithmetic circuit to perform addition and subtraction operations on N n-bit unsigned integers encoded in quantum registers, and it is compatible with…

We propose two tiers of modifications to FPGA logic cell architecture to deliver a variety of performance and utilization benefits with only minor area overheads. In the irst tier, we augment existing commercial logic cell datapaths with a…

We design quantum circuits by using the standard cell approach borrowed from classical circuit design, which can speed-up the layout of circuits with a regular structure. Our standard cells are general and can be used for all types of…

We introduce a novel logic style with self-checking capability to enhance hardware reliability at logic level. The proposed logic cells have two-rail inputs/outputs, and the functionality for each rail of outputs enables construction of…