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Digital Signal Processing functions are widely used in real time high speed applications. Those functions are generally implemented either on ASICs with inflexibility, or on FPGAs with bottlenecks of relatively smaller utilization factor or…
A digital frequency multiplexing (DfMUX) system has been developed and used to tune large arrays of transition edge sensor (TES) bolometers read out with SQUID arrays for mm-wavelength cosmology telescopes. The DfMUX system multiplexes the…
We introduce and experimentally characterize a general purpose device for signal processing in circuit quantum electrodynamics systems. The device is a broadband two-port microwave circuit element with three modes of operation: it can…
Superconducting quantum computers have emerged as a leading platform for next-generation computing, offering exceptional scalability and unprecedented computational speeds. However, scaling these systems to millions of qubits for practical…
The CMS experiment at the CERN LHC will be upgraded to accommodate the 5-fold increase in the instantaneous luminosity expected at the High-Luminosity LHC (HL-LHC). Concomitant with this increase will be an increase in the number of…
Solid-state quantum computers require classical electronics to control and readout individual qubits and to enable fast classical data processing [1-3]. Integrating both subsystems at deep cryogenic temperatures [4], where solid-state…
This work presents the design and preliminary performance of a highly-multiplexed superconducting detector readout. The readout system is implemented on the Xilinx ZCU111 RFSoC Evaluation Board. The current design uses 12% of the DSPs, 60%…
Heterogeneous multi-core architectures combine a few "host" cores, optimized for single-thread performance, with many small energy-efficient "accelerator" cores for data-parallel processing, on a single chip. Offloading a computation to the…
In the context of the High-Luminosity (HL) upgrade of the LHC, many custom ATCA electronics boards are being designed containing heterogeneous System-on-Chip (SoC) devices, more specifically the Xilinx Zynq UltraScale+ (ZUS+) family. While…
Dalek is an experimental compute cluster designed to evaluate the performance of heterogeneous, consumer-grade hardware for software design, prototyping, and algorithm development. In contrast to traditional computing centers that rely on…
Many HPC applications can be expressed as mixed-mode computations, in which each node of a computational DAG is itself a parallel computation that can be molded at runtime to allocate different amounts of processing resources. At the same…
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities. While…
Heterogeneous computing is emerging as a mandatory requirement for power-efficient system design. With this aim, modern heterogeneous platforms like Zynq All-Programmable SoC, that integrates ARM-based SMP and programmable logic, have been…
Current control techniques for cryogenically cooled qubits are realized with coaxial cables, posing multiple challenges in terms of cost, thermal load, size, and long-term scalability. Emerging approaches to tackle this issue include…
A data acquisition (DAQ) system is described which will be used for the next generation of prototype calorimeters using particle flow algorithms for the International Linear Collider (ILC). The design is sufficiently generic and scalable…
Superconducting electronics are among the most promising alternatives to conventional CMOS technology thanks to the ultra-fast speed and ultra-high energy efficiency of the superconducting devices. Having a cryogenic control processor is…
A robust cryogenic infrastructure in form of a wired, thermally optimized dilution refrigerator is essential for present and future solid-state based quantum processors. Here, we engineer an extensible cryogenic setup, which minimizes…
The demand for hundreds of tightly synchronized channels operating at tens of MSPS in ultrasound systems exceeds conventional low-voltage differential signaling links' bandwidth, pin count, and latency. Although the JESD204B serial…
Purpose: The purpose of this article is to present a system that enhances the security, efficiency, and reconfigurability of an Internet-of-Things (IoT) system used for surveillance and monitoring. Methods: A Multi-Processor System-On-Chip…
As the one-chip integration of HW-modules designed by different companies becomes more and more popular reliability of a HW-design and evaluation of the timing behavior during the prototype stage are absolutely necessary. One way to…