Related papers: Approximate Scan Flip-flop to Reduce Functional Pa…

Fan-out wafer-level packaging (FOWLP) addresses the demand for higher interconnect densities by offering reduced form factor, improved signal integrity, and enhanced performance. However, FOWLP faces manufacturing challenges such as…

Non-volatile flip-flops (NVFFs) using power gating techniques promise to overcome the soaring leakage power consumption issue with the scaling of CMOS technology. Magnetic tunnel junction (MTJ) is a good candidate for constructing the NVFF…

General Matrix Multiplication (GEMM) is a fundamental operation widely used in scientific computations. Its performance and accuracy significantly impact the performance and accuracy of applications that depend on it. One such application…

Extensive set of tests on different platforms indicated that there is a performance drop of current standard de facto software library for the Discrete Fourier Transform (DFT) in case of large 2D array sizes (larger than 16384x16384).…

Fast Fourier transform (FFT) of large number of samples requires huge hardware resources of field programmable gate arrays (FPGA), which needs more area and power. In this paper, we present an area efficient architecture of FFT processor…

We present a scalable in-pixel processing architecture that can reduce the data throughput by 10X and consume less than 30 mW per megapixel at the imager frontend. Unlike the state-of-the-art (SOA) analog process-in-pixel (PIP) that…

Photonic computing has emerged as a promising platform for accelerating computational tasks with high degrees of parallelism, such as image processing and neural network. We present meta-DFT (discrete Fourier transform), a single layer…

The rapid adaptation of data driven AI models, such as deep learning inference, training, Vision Transformers (ViTs), and other HPC applications, drives a strong need for runtime precision configurable different non linear activation…

Development of large computerized systems requires both combinational and sequential circuits. Registers and counters are two important examples of sequential circuits, which are widely used in practical applications like CPUs. The basic…

In this study the possibility of combining commercial Scanning Force Microscopes (SFM) with stretching devices for the investigation of microscopic surface changes during stepwise elongation is investigated. Different types of stretching…

In this letter we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of a HEMT and a FinFET, to obtain excellent performance and good off state control. Followed by the description of the…

With the increasing demand for multi-carrier communication in high-mobility scenarios, it is urgent to design new multi-carrier communication waveforms that can resist large delay-Doppler spreads. Various multi-carrier waveforms in the…

We have integrated single and coupled superconducting transmon qubits into flip-chip modules. Each module consists of two chips -- one quantum chip and one control chip -- that are bump-bonded together. We demonstrate time-averaged…

We investigate nano scanning in tapping mode atomic force microscopy (AFM) under quality (Q) control via numerical simulations performed in SIMULINK. We focus on the simulation of whole scan process rather than the simulation of cantilever…

Increasing development in embedded systems, VLSI and processor design have given rise to increased demands from the system in terms of power, speed, area, throughput etc. Most of the sophisticated embedded system applications consist of…

The matrix-free gather-batched-GEMM-scatter pattern eliminates global stiffness assembly for three-dimensional SIMP topology optimization, but the conventional three-stage implementation forces avoidable DRAM traffic between stages. We…

In this paper, an optimized efficient VLSI architecture of a pipeline Fast Fourier transform (FFT) processor capable of producing the reverse output order sequence is presented. Paper presents Radix-2 multipath delay architecture for FFT…

In this paper, we introduce DFSSD, a novel logic locking solution for sequential and FSM circuits with a restricted (locked) access to the scan chain. DFSSD combines two techniques for obfuscation: (1) Deep Faults, and (2) Shallow State…

Conventional dual-frequency fringe projection algorithm often suffers from phase unwrapping failure when the frequency ratio between the high frequency and the low one is too large. Zhang et.al. proposed an enhanced two-frequency…

A method for mitigating the readout delay characteristic of Bragg-based atom interferometry is presented, utilizing an asymmetric Mach-Zehnder interferometer sequence to generate spatial fringes that are read out while still overlapped. The…