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The interplay between timeliness and rate efficiency is investigated in packet erasure broadcast channels with feedback. A scheduling framework is proposed in which coding actions, as opposed to users, are scheduled to attain desired…

Information Theory · Computer Science 2021-03-11 Xingran Chen , Renpu Liu , Shaochong Wang , Shirin Saeedi Bidokhti

Over the past two decades, the storage capacity and access bandwidth of main memory have improved tremendously, by 128x and 20x, respectively. These improvements are mainly due to the continuous technology scaling of DRAM (dynamic…

Hardware Architecture · Computer Science 2017-12-25 Kevin K. Chang

The performance of neural decoders can degrade over time due to nonstationarities in the relationship between neuronal activity and behavior. In this case, brain-machine interfaces (BMI) require adaptation of their decoders to maintain high…

Machine Learning · Computer Science 2012-06-19 Tayfun Gürel , Carsten Mehring

Memory tiering provides a cost-effective solution to increase memory capacity, utilization, and even bandwidth. Memory tiering relies on system software for memory profiling, detection of frequently accessed pages, and page migration. Such…

Operating Systems · Computer Science 2026-04-15 Xi Wang , Jie Liu , Shuangyan Yang , Jongryool Kim , Pengfei Su , Dong Li

State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is…

Hardware Architecture · Computer Science 2022-09-13 Saeed Seyedfaraji , Baset Mesgari , Semeen Rehman

The ubiquity of vision transformers (ViTs) for various edge applications, including personalized learning, has created the demand for on-device fine-tuning. However, training with the limited memory and computation power of edge devices…

Computer Vision and Pattern Recognition · Computer Science 2024-05-21 Sreetama Sarkar , Souvik Kundu , Kai Zheng , Peter A. Beerel

Memory tiering systems achieve memory scaling by adding multiple tiers of memory wherein different tiers have different access latencies and bandwidth. For maximum performance, frequently accessed (hot) data must be placed close to the host…

Operating Systems · Computer Science 2025-04-29 Konstantinos Kanellis , Sujay Yadalam , Fanchao Chen , Michael Swift , Shivaram Venkataraman

Multi-core neuromorphic processors are becoming increasingly significant due to their energy-efficient local computing and scalable modular architecture, particularly for event-based processing applications. However, minimizing the cost of…

Hardware Architecture · Computer Science 2024-11-19 Zhe Su , Aron Bencsik , Giacomo Indiveri , Davide Bertozzi

High capacity and scalable memory systems play a vital role in enabling our desktops, smartphones, and pervasive technologies like Internet of Things (IoT). Unfortunately, memory systems are becoming increasingly prone to faults. This is…

Hardware Architecture · Computer Science 2019-09-04 Prashant J. Nair

A major hurdle in brain-machine interfaces (BMI) is the lack of an implantable neural interface system that remains viable for a lifetime. This paper explores the fundamental system design trade-offs and ultimate size, power, and bandwidth…

Neurons and Cognition · Quantitative Biology 2013-07-09 Dongjin Seo , Jose M. Carmena , Jan M. Rabaey , Elad Alon , Michel M. Maharbiz

Software aging is a phenomenon that refers to progressive performance degradation or transient failures or even crashes in long running software systems such as web servers. It mainly occurs due to the deterioration of operating system…

Artificial Intelligence · Computer Science 2012-06-08 G. Sumathi , R. Raju

Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the…

Hardware Architecture · Computer Science 2022-02-25 Corentin Ferry , Tomofumi Yuki , Steven Derrien , Sanjay Rajopadhye

Triangle counting (TC) is a fundamental problem in graph analysis and has found numerous applications, which motivates many TC acceleration solutions in the traditional computing platforms like GPU and FPGA. However, these approaches suffer…

Hardware Architecture · Computer Science 2020-07-22 Xueyan Wang , Jianlei Yang , Yinglin Zhao , Yingjie Qi , Meichen Liu , Xingzhou Cheng , Xiaotao Jia , Xiaoming Chen , Gang Qu , Weisheng Zhao

Fault-tolerant deep learning accelerator is the basis for highly reliable deep learning processing and critical to deploy deep learning in safety-critical applications such as avionics and robotics. Since deep learning is known to be…

Hardware Architecture · Computer Science 2023-12-22 Qing Zhang , Cheng Liu , Bo Liu , Haitong Huang , Ying Wang , Huawei Li , Xiaowei Li

Flexibility at hardware level is the main driving force behind adaptive systems whose aim is to realise microarhitecture deconfiguration 'online'. This feature allows the software/hardware stack to tolerate drastic changes of the workload…

Hardware Architecture · Computer Science 2016-12-28 Ana Lava , Mahdi Jelodari Mamaghani , Siamak Mohammadi , Steve Furber

To support emerging real-time monitoring and control applications, the timeliness of computation results is of critical importance to mobile-edge computing (MEC) systems. We propose a performance metric called age of task (AoT) based on the…

Signal Processing · Electrical Eng. & Systems 2019-05-29 Xianxin Song , Xiaoqi Qin , Yunzheng Tao , Baoling Liu , Ping Zhang

In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities and defects of emerging technologies used in advanced…

Recurrent transducer models have emerged as a promising solution for speech recognition on the current and next generation smart devices. The transducer models provide competitive accuracy within a reasonable memory footprint alleviating…

Brain-computer interfaces (BCIs) allow direct communication between the brain and external devices, frequently using electroencephalography (EEG) to record neural activity. Dimensionality reduction and structured regularization are…

Signal Processing · Electrical Eng. & Systems 2025-11-07 Arne Van Den Kerchove , Hakim Si-Mohammed , François Cabestaing , Marc M. Van Hulle

Sorting is a fundamental operation across numerous computational domains. Traditionally, this process involves transferring data from main memory to a processing unit for sorting, followed by writing the sorted data back to memory. This…

Hardware Architecture · Computer Science 2026-05-18 Narendra Singh Dhakad , Santosh Kumar Vishvakarma