Related papers: Low-power In-pixel Computing with Current-modulate…
An array of DEPFET pixels is one of several concepts to implement an active pixel sensor. Similar to PNCCD and SDD detectors, the typically 0.45 mm thick silicon sensor is fully depleted by the principle of sideward depletion. They have…
The rise of artificial intelligence has triggered exponential growth in data volume, demanding rapid and efficient processing. High-speed, energy-efficient, and parallel-scalable computing hardware is thus increasingly critical. We…
Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after…
The rapid surge in data generated by Internet of Things (IoT), artificial intelligence (AI), and machine learning (ML) applications demands ultra-fast, scalable, and energy-efficient hardware, as traditional von Neumann architectures face…
Recent advances in artificial intelligence, coupled with increasing data bandwidth requirements, in applications such as video processing and high-resolution sensing, have created a growing demand for high computational performance under…
Attention-based models are proliferating in the space of image analytics, including segmentation. The standard method of feeding images to transformer encoders is to divide the images into patches and then feed the patches to the model as a…
This paper proposes an low power approximate multiplier architecture for deep neural network (DNN) applications. A 4:2 compressor, introducing only a single combination error, is designed and integrated into an 8x8 unsigned multiplier. This…
Silicon photonic integrated circuits offer significant improvements in processing bandwidth, power efficiency, and low latency, addressing the needs of future microwave communication systems. Several successful applications have been…
Collocated data processing and storage are the norm in biological systems. Indeed, the von Neumann computing architecture, that physically and temporally separates processing and memory, was born more of pragmatism based on available…
Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwidths. In this work, we develop a comprehensive system-level…
This thesis develops signal-processing algorithms and implementation schemes under constraints of minimal parallelism and memory space, with the goal of improving energy efficiency of low-power computing hardware. We propose (i) a…
Processing-in-memory (PIM) has shown extraordinary potential in accelerating neural networks. To evaluate the performance of PIM accelerators, we present an ISA-based simulation framework including a dedicated ISA targeting neural networks…
In the "post-Moore era", the growing challenges in traditional computing have driven renewed interest in analog computing, leading to various proposals for the development of general-purpose analog computing (GPAC) systems. In this work, we…
Photonic computing chips have made significant progress in accelerating linear computations, but nonlinear computations are usually implemented in the digital domain, which introduces additional system latency and power consumption, and…
Coherent photonic computing uses both the phase and amplitude of light to implement linear operations such as dot products and matrix multiplication but requires phase stability between the interfering paths. This poses a challenge for such…
A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 102GOPS running at 204MHz. To minimize energy consumption…
Due to challenging efficiency limits facing conventional and unconventional electronic architectures, information processors based on photonics have attracted renewed interest. Research communities have yet to settle on definitive…
Current learned image compression models typically exhibit high complexity, which demands significant computational resources. To overcome these challenges, we propose an innovative approach that employs hierarchical feature extraction…
The existing ATLAS Tracker will be at its functional limit for particle fluences of 10^15 neq/cm^2 (LHC). Thus for the upgrades at smaller radii like in the case of the planned Insertable B-Layer (IBL) and for increased LHC luminosities…
The multi-pixel photon counter (MPPC) is a newly developed photodetector with an excellent photon counting capability. It also has many attractive features such as small size, high gain, low operation voltage and power consumption, and…