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High Bandwidth Memory (HBM) provides massive aggregated memory bandwidth by exposing multiple memory channels to the processing units. To achieve high performance, an accelerator built on top of an FPGA configured with HBM (i.e., FPGA-HBM…

Hardware Architecture · Computer Science 2021-10-13 Kexin Li , Chenhao Liu , Zhiyuan Shao , Zeke Wang , Minkang Wu , Jiajie Chen , Xiaofei Liao , Hai Jin

Modern Graphics Processing Units (GPUs) are now considered accelerators for general purpose computation. A tight interaction between the GPU and the interconnection network is the strategy to express the full potential on capability…

FPGA is appropriate for fix-point neural networks computing due to high power efficiency and configurability. However, its design must be intensively refined to achieve high performance using limited hardware resources. We present an…

Hardware Architecture · Computer Science 2022-01-03 Qingyang Yi , Heming Sun , Masahiro Fujita

The use of FPGAs for efficient graph processing has attracted significant interest. Recent memory subsystem upgrades including the introduction of HBM in FPGAs promise to further alleviate memory bottlenecks. However, modern multi-channel…

Hardware Architecture · Computer Science 2022-03-08 Xinyu Chen , Yao Chen , Feng Cheng , Hongshi Tan , Bingsheng He , Weng-Fai Wong

Recent trends in business and technology (e.g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph…

Databases · Computer Science 2021-02-09 Jonas Dann , Daniel Ritter , Holger Fröning

Graphics Processing Units (GPUs) are currently the dominating programmable architecture for Deep Learning (DL) accelerators. The adoption of Field Programmable Gate Arrays (FPGAs) in DL accelerators is however getting momentum. In this…

Hardware Architecture · Computer Science 2021-02-03 Walther Carballo-Hernández , Maxime Pelcat , François Berry

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA…

Networking and Internet Architecture · Computer Science 2025-04-17 Zhaoyang Han , Andrew Briasco-Stewart , Michael Zink , Miriam Leeser

Processing-In-Memory (PIM) architectures offer a promising approach to accelerate Graph Neural Network (GNN) training and inference. However, various PIM devices such as ReRAM, FeFET, PCM, MRAM, and SRAM exist, with each device offering…

FPGAs are starting to be enhanced with High Bandwidth Memory (HBM) as a way to reduce the memory bandwidth bottleneck encountered in some applications and to give the FPGA more capacity to deal with application state. However, the…

Hardware Architecture · Computer Science 2020-05-12 Zeke Wang , Hongjing Huang , Jie Zhang , Gustavo Alonso

Deep neural network (DNN) inference relies increasingly on specialized hardware for high computational efficiency. This work introduces a field-programmable gate array (FPGA)-based dynamically configurable accelerator featuring systolic…

Hardware Architecture · Computer Science 2025-10-10 Anastasios Petropoulos , Theodore Antonakopoulos

In natural language processing (NLP), the "Transformer" architecture was proposed as the first transduction model replying entirely on self-attention mechanisms without using sequence-aligned recurrent neural networks (RNNs) or convolution,…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-07-20 Bingbing Li , Santosh Pandey , Haowen Fang , Yanjun Lyv , Ji Li , Jieyang Chen , Mimi Xie , Lipeng Wan , Hang Liu , Caiwen Ding

The emergence of P4, a domain specific language, coupled to PISA, a domain specific architecture, is revolutionizing the networking field. P4 allows to describe how packets are processed by a programmable data plane, spanning ASICs and…

Hardware Architecture · Computer Science 2020-04-17 Thomas Luinaud , Thibaut Stimpfling , Jeferson Santiago da Silva , Yvon Savaria , J. M. Pierre Langlois

Both industry and academia have extensively investigated hardware accelerations. In this work, to address the increasing demands in computational capability and memory requirement, we propose structured weight matrices (SWM)-based…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-05-01 Caiwen Ding , Ao Ren , Geng Yuan , Xiaolong Ma , Jiayu Li , Ning Liu , Bo Yuan , Yanzhi Wang

The rapid advancements in artificial intelligence (AI), particularly the Large Language Models (LLMs), have profoundly affected our daily work and communication forms. However, it is still a challenge to deploy LLMs on resource-constrained…

Hardware Architecture · Computer Science 2025-03-03 Mingqiang Huang , Ao Shen , Kai Li , Haoxiang Peng , Boyu Li , Yupeng Su , Hao Yu

Field Programmable Gate Arrays (FPGAs) have recently been increasingly used for highly-parallel processing of compute intensive tasks. This paper introduces an FPGA hardware platform architecture that is PC-based, allows for fast…

Hardware Architecture · Computer Science 2007-05-23 Andreas Weisensee , Darran Nathan

This work presents a heterogeneous communication library for clusters of processors and FPGAs. This library, Shoal, supports the Partitioned Global Address Space (PGAS) memory model for applications. PGAS is a shared memory model for…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-04-27 Varun Sharma , Paul Chow

For several decades, the CPU has been the standard model to use in the majority of computing. While the CPU does excel in some areas, heterogeneous computing, such as reconfigurable hardware, is showing increasing potential in areas like…

Hardware Architecture · Computer Science 2021-04-21 Carl-Johannes Johnsen , Alberte Thegler , Kenneth Skovhede , Brian Vinter

Field Programmable Gate Arrays (FPGAs) plays an increasingly important role in data sampling and processing industries due to its highly parallel architecture, low power consumption, and flexibility in custom algorithms. Especially, in the…

Computer Vision and Pattern Recognition · Computer Science 2017-11-17 Yufeng Hao

Fully Homomorphic Encryption (FHE) is a technique that allows arbitrary computations to be performed on encrypted data without the need for decryption, making it ideal for securing many emerging applications. However, FHE computation is…

Graph Neural Networks (GNNs) have shown great success in many applications such as recommendation systems, molecular property prediction, traffic prediction, etc. Recently, CPU-FPGA heterogeneous platforms have been used to accelerate many…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-12-23 Yi-Chien Lin , Bingyi Zhang , Viktor Prasanna