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FPGA technology can offer significantly hi\-gher performance at much lower power consumption than is available from CPUs and GPUs in many computational problems. Unfortunately, programming for FPGA (using ha\-rdware description languages,…

While FPGA accelerator boards and their respective high-level design tools are maturing, there is still a lack of multi-FPGA applications, libraries, and not least, benchmarks and reference implementations towards sustained HPC usage of…

Motivated by the stringent requirements of the Upstream Pixel (UP) tracker in the LHCb Upgrade II and the Inner Tracking detector (ITK) of the Circular Electron Positron Collider, the COFFEE series of pixel sensor chips have been developed…

Fast, high-fidelity, and quantum nondemolition (QND) qubit readout is an essential element of quantum information processing. For superconducting qubits, state-of-the-art readout is based on a dispersive cross-Kerr coupling between a qubit…

In recent years the computational capacity of single Field Programmable Gate Arrays (FPGA) devices as well as their versatility has increased significantly. Adding to that the High Level Synthesis frameworks allowing to program such…

Rising connectivity in vehicles is enabling new capabilities like connected autonomous driving and advanced driver assistance systems (ADAS) for improving the safety and reliability of next-generation vehicles. This increased access to…

Nonbinary LDPC codes have shown superior performance close to the Shannon limit. Compared to binary LDPC codes of similar lengths, they can reach orders of magnitudes lower error rate. However, multitude of design freedoms of nonbinary LDPC…

RC4 can be made more secured if an additional RC4-like Post-KSA Random Shuffing (PKRS) process is introduced between KSA and PRGA. It can also be made significantly faster if RC4 bytes are processed in a FPGA embedded system using multiple…

Recent years have shown an increased use of silicon photo-multipliers (SiPM) in experiments as they are of reasonable cost, have relatively low power consumption and are easily available in a variety of form factors allowing for a large…

Real-time Deep Neural Network (DNN) inference with low-latency requirement has become increasingly important for numerous applications in both cloud computing (e.g., Apple's Siri) and edge computing (e.g., Google/Waymo's driverless car).…

An FPGA based digital signal processing (DSP) system for biasing and reading out multiplexed bolometric detectors for mm-wavelength telescopes is presented. This readout system is being deployed for balloon-borne and ground based cosmology…

Three key metrics for readout systems in quantum processors are measurement speed, fidelity and footprint. Fast high-fidelity readout enables mid-circuit measurements, a necessary feature for many dynamic algorithms and quantum error…

Modern chip design is complex, and there is a crucial need for early-stage prediction of key design-quality metrics like timing and routing congestion directly from Verilog code (a commonly used programming language for hardware design). It…

Over the past decade, kinetic inductance detectors (KIDs) have emerged as a viable superconducting technology for astrophysics at millimeter and submillimeter wavelengths. KIDs spanning 210 - 850 GHz across seven instrument modules will be…

Evolutionary algorithms can outperform conventional placement algorithms such as simulated annealing, analytical placement as well as manual placement on metrics such as runtime, wirelength, pipelining cost, and clock frequency when mapping…

In this paper we report on the timing resolution of the first production of 50 micro-meter thick Ultra-Fast Silicon Detectors (UFSD) as obtained in a beam test with pions of 180 GeV/c momentum. UFSD are based on the Low-Gain Avalanche…

A number of modern millimeter, sub-millimeter, and far-infrared detectors are read out using superconducting microwave (1-10GHz) resonators. The main detector technologies are Transition Edge Sensors, read out using Microwave SQUID…

For massive multiple-input multiple-output (MIMO) systems, linear minimum mean-square error (MMSE) detection has been shown to achieve near-optimal performance but suffers from excessively high complexity due to the large-scale matrix…

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a…

This technical report documents the development of novel Layout Analysis models integrated into the Docling document-conversion pipeline. We trained several state-of-the-art object detectors based on the RT-DETR, RT-DETRv2 and DFINE…