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Multicore shared cache processors pose a challenge for designers of embedded systems who try to achieve minimal and predictable execution time of workloads consisting of several jobs. To address this challenge the cache is statically…

Data Structures and Algorithms · Computer Science 2012-11-26 Avinatan Hassidim , Haim Kaplan , Omry Tuval

Multicore is an integrated circuit chip that uses two or more computational engines (cores) places in a single processor. This new approach is used to split the computational work of a threaded application and spread it over multiple…

Operating Systems · Computer Science 2019-10-03 Reza Fotohi , Mehdi Effatparvar , Fateme Sarkohaki , Shahram Behzad , Jaber Hoseini balov

Partitioning graphs into blocks of roughly equal size such that few edges run between blocks is a frequently needed operation in processing graphs. Recently, size, variety, and structural complexity of these networks has grown dramatically.…

Data Structures and Algorithms · Computer Science 2018-10-16 Yaroslav Akhremtsev , Peter Sanders , Christian Schulz

It is an increasingly important issue to reduce the energy consumption of computing systems. In this paper, we consider partition based energy-aware scheduling of periodic real-time tasks on multicore processors. The scheduling exploits…

Distributed, Parallel, and Cluster Computing · Computer Science 2016-11-17 Hongtao Huang , Feng Xia , Jijie Wang , Siyu Lei , Guowei Wu

Modern large-scale scientific applications consist of thousands to millions of individual tasks. These tasks involve not only computation but also communication with one another. Typically, the communication pattern between tasks is sparse…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-04-03 Christian Schulz , Henning Woydt

An effective way to improve energy efficiency is to throttle hardware resources to meet a certain performance target, specified as a QoS constraint, associated with all applications running on a multicore system. Prior art has proposed…

Hardware Architecture · Computer Science 2019-11-14 Mehrzad Nejat , Madhavan Manivannan , Miquel Pericas , Per Stenstrom

In-network caching is recognized as an effective solution to offload content servers and the network. A cache service provider (SP) always has incentives to better utilize its cache resources by taking into account diverse roles that…

Networking and Internet Architecture · Computer Science 2017-12-12 Weibo Chu , Mostafa Dehghan , John C. S. Lui , Don Towsley , Zhi-Li Zhang

Cause-effect chains, as a widely used modeling method in real-time embedded systems, are extensively applied in various safety-critical domains. End-to-end latency, as a key real-time attribute of cause-effect chains, is crucial in many…

Systems and Control · Electrical Eng. & Systems 2026-01-29 Yixuan Zhu , Yinkang Gao , Bo Zhang , Xiaohang Gong , Binze Jiang , Lei Gong , Wenqi Lou , Teng Wang , Chao Wang , Xi Li , Xuehai Zhou

Reducing the average memory access time is crucial for improving the performance of applications running on multi-core architectures. With workload consolidation this becomes increasingly challenging due to shared resource contention.…

Hardware Architecture · Computer Science 2021-02-24 Nadja Ramhöj Holtryd , Madhavan Manivannan , Per Stenström , Miquel Pericàs

All-pairs compute problems apply a user-defined function to each combination of two items of a given data set. Although these problems present an abundance of parallelism, data reuse must be exploited to achieve good performance. Several…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-09-11 Stijn Heldens , Pieter Hijma , Ben van Werkhoven , Jason Maassen , Henri Bal , Rob van Nieuwpoort

This paper presents a new strategy for scheduling soft real-time tasks on multiple identical cores. The proposed approach is based on partitioned CPU reservations and it uses a reclaiming mechanism to reduce the number of missed deadlines.…

Operating Systems · Computer Science 2019-05-01 Houssam Eddine Zahaf , Giuseppe Lipari , Luca Abeni , Houssam-Eddine Zahaf

Modern hardware systems are heavily underutilized when running large-scale graph applications. While many in-memory graph frameworks have made substantial progress in optimizing these applications, we show that it is still possible to…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-01-15 Yunming Zhang , Vladimir Kiriansky , Charith Mendis , Matei Zaharia , Saman Amarasinghe

Multicore processors constitute the main architecture choice for modern computing systems in different market segments. Despite their benefits, the contention that naturally appears when multiple applications compete for the use of shared…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-02-13 Adrián García-García , Juan Carlos Sáez , Fernando Castro , Manuel Prieto-Matías

The system-level cache is a critical resource shared by processor cores and domain-specific accelerators in heterogeneous systems on chips (SoCs). The strict QoS requirements of accelerators, such as deadlines, can lead to severe…

Hardware Architecture · Computer Science 2026-05-21 Ayushi Agarwal , Anannya Mathur , Preeti Ranjan Panda

Common implementations of core memory allocation components, like the Linux buddy system, handle concurrent allocation/release requests by synchronizing threads via spin-locks. This approach is clearly not prone to scale with large thread…

Distributed, Parallel, and Cluster Computing · Computer Science 2018-05-22 Romolo Marotta , Mauro Ianni , Alessandro Pellegrini , Andrea Scarselli , Francesco Quaglia

Major chip manufacturers have all introduced Multithreaded processors. These processors are used for running a variety of workloads. Efficient resource utilization is an important design aspect in such processors. Particularly, it is…

Performance · Computer Science 2019-08-13 Murthy Durbhakula

Utilizing on-chip caches in embedded multiprocessor-system-on-a-chip (MPSoC) based systems is critical from both performance and power perspectives. While most of the prior work that targets at optimizing cache behavior are performed at…

Hardware Architecture · Computer Science 2011-11-09 Mahmut Kandemir , Guilin Chen

Graphics Processing Units (GPUs) consisting of Streaming Multiprocessors (SMs) achieve high throughput by running a large number of threads and context switching among them to hide execution latencies. The number of thread blocks, and hence…

Hardware Architecture · Computer Science 2015-06-08 Vishwesh Jatala , Jayvant Anantpur , Amey Karkare

Collaborative Edge Computing (CEC) is a new edge computing paradigm that enables neighboring edge servers to share computational resources with each other. Although CEC can enhance the utilization of computational resources, it still…

Networking and Internet Architecture · Computer Science 2025-02-18 Xingqiu He , Chaoqun You , Tony Q. S. Quek

This article describes a geometric partitioning software that can be used for quick computation of data partitions on many-core HPC machines. It is most suited for dynamic applications with load distributions that vary with time.…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-08-19 Aparna Sasidharan