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We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints used in the scheduling step.…

Hardware Architecture · Computer Science 2016-08-16 Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin

Graphics Processing Units (GPUs) have become the leading hardware accelerator for deep learning applications and are used widely in training and inference of transformers; transformers have achieved state-of-the-art performance in many…

Hardware Architecture · Computer Science 2024-05-03 Andy He , Darren Key , Mason Bulling , Andrew Chang , Skyler Shapiro , Everett Lee

The integral image, an intermediate image representation, has found extensive use in multi-scale local feature detection algorithms, such as Speeded-Up Robust Features (SURF), allowing fast computation of rectangular features at constant…

Computer Vision and Pattern Recognition · Computer Science 2015-10-20 Shoaib Ehsan , Adrian F. Clark , Naveed ur Rehman , Klaus D. McDonald-Maier

Embedded vision systems need efficient and robust image processing algorithms to perform real-time, with resource-constrained hardware. This research investigates image processing algorithms, specifically edge detection, corner detection,…

Image and Video Processing · Electrical Eng. & Systems 2026-01-13 Soundes Oumaima Boufaida , Abdemadjid Benmachiche , Majda Maatallah

The escalating data volume and complexity resulting from the rapid expansion of artificial intelligence (AI), internet of things (IoT) and 5G/6G mobile networks is creating an urgent need for energy-efficient, scalable computing hardware.…

Image stitching aims at stitching the images taken from different viewpoints into an image with a wider field of view. Existing methods warp the target image to the reference image using the estimated warp function, and a homography is one…

Computer Vision and Pattern Recognition · Computer Science 2021-12-14 Hyeokjun Kweon , Hyeonseong Kim , Yoonsu Kang , Youngho Yoon , Wooseong Jeong , Kuk-Jin Yoon

The performance of graph programs depends highly on the algorithm, the size and structure of the input graphs, as well as the features of the underlying hardware. No single set of optimizations or one hardware platform works well across all…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-01-11 Ajay Brahmakshatriya , Yunming Zhang , Changwan Hong , Shoaib Kamil , Julian Shun , Saman Amarasinghe

Accelerating Human Action Recognition (HAR) efficiently for real-time surveillance and robotic systems on edge chips remains a challenging research field, given its high computational and memory requirements. This paper proposed an…

Computer Vision and Pattern Recognition · Computer Science 2023-11-08 Azzam Alhussain , Mingjie Lin

In this paper, we describe a high-level synthesis (HLS) tool that automatically allows area/throughput trade-offs for implementing streaming task graphs (STG). Our tool targets a massively parallel processor array (MPPA) architecture, very…

Hardware Architecture · Computer Science 2016-06-14 Hossein Omidian , Guy G. F. Lemieux

Efficient and real time segmentation of color images has a variety of importance in many fields of computer vision such as image compression, medical imaging, mapping and autonomous navigation. Being one of the most computationally…

Computer Vision and Pattern Recognition · Computer Science 2017-10-09 Roopal Nahar , Akanksha Baranwal , K. Madhava Krishna

Plenty of research efforts have been devoted to FPGA-based acceleration, due to its low latency and high energy efficiency. However, using the original low-level hardware description languages like Verilog to program FPGAs requires…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-10-20 Ruoshi Li , Hongjing Huang , Zeke Wang , Zhiyuan Shao , Xiaofei Liao , Hai Jin

FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high quality of results.…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-06-15 Marius Meyer , Tobias Kenter , Christian Plessl

As program workloads (e.g., AI) increase in size and algorithmic complexity, the primary challenge lies in their high dimensionality, encompassing computing cores, array sizes, and memory hierarchies. To overcome these obstacles, innovative…

Hardware Architecture · Computer Science 2025-10-10 Jinwei Tang , Jiayin Qin , Nuo Xu , Pragnya Sudershan Nalla , Yu Cao , Yang , Zhao , Caiwen Ding

Recently, some hypergraph-based methods have been proposed to deal with the problem of model fitting in computer vision, mainly due to the superior capability of hypergraph to represent the complex relationship between data points. However,…

Computer Vision and Pattern Recognition · Computer Science 2020-02-14 Shuyuan Lin , Guobao Xiao , Yan Yan , David Suter , Hanzi Wang

FPGAs are well established in the signal processing domain, where their fine-grained programmable nature allows the inherent parallelism in these applications to be exploited for enhanced performance. As architectures have evolved, FPGA…

Hardware Architecture · Computer Science 2017-10-18 Abdullah Al-Dujaili , Suhaib A. Fahmy

High-level synthesis (HLS) accelerates FPGA design by rapidly generating diverse implementations using optimization directives. However, even with cycle-accurate C/RTL co-simulation, the reported clock cycles often differ significantly from…

Hardware Architecture · Computer Science 2025-04-18 Jiho Kim , Cong Hao

Accelerating Machine Learning (ML) workloads requires efficient methods due to their large optimization space. Autotuning has emerged as an effective approach for systematically evaluating variations of implementations. Traditionally,…

Hardware Architecture · Computer Science 2026-01-30 Rebecca Pelke , Nils Bosbach , Lennart M. Reimann , Rainer Leupers

The most important way to achieve higher performance in computer systems is through heterogeneous computing, i.e., by adopting hardware platforms containing more than one type of processor, such as CPUs, GPUs, and FPGAs. Several types of…

Software Engineering · Computer Science 2020-05-19 Hugo Andrade , Ivica Crnkovic , Jan Bosch

Future computing systems, from handhelds to supercomputers, will undoubtedly be more parallel and heterogeneous than todays systems to provide more performance and energy efficiency. Thus, GPUs are increasingly being used to accelerate…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-10-18 Saeed Taheri , Apan Qasem , Martin Burtscher

This work is concerned with the evaluation of the performance of parallelization of learning and tuning processes for image classification and large language models. For machine learning model in image recognition, various parallelization…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-03-20 Marcin Lawenda , Krzesimir Samborski , Kyrylo Khloponin , Łukasz Szustak
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