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Modern general-purpose accelerators integrate a large number of programmable area- and energy-efficient processing elements (PEs), to deliver high performance while meeting stringent power delivery and thermal dissipation constraints. In…

Hardware Architecture · Computer Science 2025-11-11 Luca Colagrande , Jayanth Jonnalagadda , Luca Benini

Matrix engines or units, in different forms and affinities, are becoming a reality in modern processors; CPUs and otherwise. The current and dominant algorithmic approach to Deep Learning merits the commercial investments in these units,…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-03-02 Jens Domke , Emil Vatai , Aleksandr Drozd , Peng Chen , Yosuke Oyama , Lingqi Zhang , Shweta Salaria , Daichi Mukunoki , Artur Podobas , Mohamed Wahib , Satoshi Matsuoka

An alias table is a data structure that allows for efficiently drawing weighted random samples in constant time and can be constructed in linear time. The PSA algorithm by H\"ubschle-Schneider and Sanders is able to construct alias tables…

Data Structures and Algorithms · Computer Science 2022-05-24 Hans-Peter Lehmann , Lorenz Hübschle-Schneider , Peter Sanders

Efficient execution of parameter sensitivity analysis (SA) is critical to allow for its routinely use. The pathology image processing application investigated in this work processes high-resolution whole-slide cancer tissue images from…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-11-01 Eduardo Scartezini , Willian Barreiros , Tahsin Kurc , Jun Kong , Alba C. M. A. Melo , Joel Saltz , George Teodoro

Serverless computing is increasingly adopted for its ability to manage complex, event-driven workloads without the need for infrastructure provisioning. However, traditional resource allocation in serverless platforms couples CPU and…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-03-03 Lingxiao Jin , Zinuo Cai , Zebin Chen , Hongyu Zhao , Ruhui Ma

Due to their growing popularity and computational cost, deep neural networks (DNNs) are being targeted for hardware acceleration. A popular architecture for DNN acceleration, adopted by the Google Tensor Processing Unit (TPU), utilizes a…

Machine Learning · Computer Science 2018-02-20 Jeff Zhang , Tianyu Gu , Kanad Basu , Siddharth Garg

AI acceleration has been dominated by GPUs, but the growing need for lower latency, energy efficiency, and fine-grained hardware control exposes the limits of fixed architectures. In this context, Field-Programmable Gate Arrays (FPGAs)…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-11-18 Arturo Urías Jiménez

Responding to the "datacenter tax" and "killer microseconds" problems for datacenter applications, diverse solutions including Smart NIC-based ones have been proposed. Nonetheless, they often suffer from high overhead of communications over…

Hardware Architecture · Computer Science 2022-10-19 Yifan Yuan , Jinghan Huang , Yan Sun , Tianchen Wang , Jacob Nelson , Dan R. K. Ports , Yipeng Wang , Ren Wang , Charlie Tai , Nam Sung Kim

Emerging ReRAM-based accelerators process neural networks via analog Computing-in-Memory (CiM) for ultra-high energy efficiency. However, significant overhead in peripheral circuits and complex nonlinear activation modes constrain system…

Hardware Architecture · Computer Science 2024-12-31 Peng Dang , Huawei Li , Wei Wang

In this work, we introduce a Self-Aware Polymorphic Architecture (SAPA) design approach to support emerging context-aware applications and mitigate the programming challenges caused by the ever-increasing complexity and heterogeneity of…

Hardware Architecture · Computer Science 2018-02-15 Michel A. Kinsy , Mihailo Isakov , Alan Ehret , Donato Kava

Today, using multiple heterogeneous accelerators efficiently from applications and high-level frameworks, such as TensorFlow and Caffe, poses significant challenges in three respects: (a) sharing accelerators, (b) allocating available…

Systems and Control · Electrical Eng. & Systems 2023-05-03 Manos Pavlidakis , Stelios Mavridis , Antony Chazapis , Giorgos Vasiliadis , Angelos Bilas

Low-rank adaptation (LoRA) has been prominently employed for parameter-efficient fine-tuning of large language models (LLMs). However, the limited expressive capacity of LoRA, stemming from the low-rank constraint, has been recognized as a…

Computation and Language · Computer Science 2025-03-18 Zhiwei He , Zhaopeng Tu , Xing Wang , Xingyu Chen , Zhijie Wang , Jiahao Xu , Tian Liang , Wenxiang Jiao , Zhuosheng Zhang , Rui Wang

Systolic Array (SA) architectures are well suited for accelerating matrix multiplications through the use of a pipelined array of Processing Elements (PEs) communicating with local connections and pre-orchestrated data movements. Even…

Hardware Architecture · Computer Science 2023-09-11 C. Peltekis , D. Filippas , G. Dimitrakopoulos , C. Nicopoulos

RRAM crossbars have been studied to construct in-memory accelerators for neural network applications due to their in-situ computing capability. However, prior RRAM-based accelerators show efficiency degradation when executing the popular…

Hardware Architecture · Computer Science 2024-02-01 Yifeng Zhai , Bing Li , Bonan Yan , Jing Wang

The reversed and shift (RAS) sparse array scheme, which is based on the difference and sum co-array (DSCA) and remarkably enhances the capability of identifying sources, is proposed. For the original nested array (NA) or co-prime array…

Signal Processing · Electrical Eng. & Systems 2020-11-30 Yan Zhou , Jin Li , Nieke Wei

Resistive random-access memory (ReRAM) crossbar arrays are suitable for efficient inference computations in neural networks due to their analog general matrix-matrix multiplication (GEMM) capabilities. However, traditional ReRAM-based…

Hardware Architecture · Computer Science 2024-09-26 Hery Shin , Jae-Young Kim , Donghyuk Kim , Joo-Young Kim

Data movement costs constitute a significant bottleneck in modern machine learning (ML) systems. When combined with the computational complexity of algorithms, such as neural networks, designing hardware accelerators with low energy…

Autonomous racing has advanced rapidly, particularly on scaled platforms, and software stacks must evolve accordingly. In this work, AROLA is introduced as a modular, layered software architecture in which fragmented and monolithic designs…

Robotics · Computer Science 2026-02-04 Fam Shihata , Mohammed Abdelazim , Ahmed Hussein

We propose a new ensemble prediction method, Random Subset Averaging (RSA), tailored for settings with many covariates, particularly in the presence of strong correlations. RSA constructs candidate models via binomial random subset strategy…

Methodology · Statistics 2025-12-30 Wenhao Cui , Jie Hu

The introduction of remote attestation (RA) schemes has allowed academia and industry to enhance the security of their systems. The commercial products currently available enable only the validation of static properties, such as…

Cryptography and Security · Computer Science 2019-04-04 Flavio Toffalini , Eleonora Losiouk , Andrea Biondo , Jianying Zhou , Mauro Conti