Related papers: TCAD Modeling of Cryogenic nMOSFET ON-State Curren…
This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from $T = 2$ K to 300 K. For a 28-nm node device, carrier…
Cryogenic characterization and modeling of 0.18um CMOS technology (1.8V and 5V) are presented in this paper. Several PMOS and NMOS transistors with different width to length ratios(W/L) were extensively characterized under various bias…
In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by…
The extremely low threshold voltage (Vth) of native MOSFETs (Vth~0V@300K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold…
Cryogenic CMOS technology (cryo-CMOS) offers a scalable solution for quantum device interface fabrication. Several previous works have studied the characterization of CMOS technology at cryogenic temperatures for various process nodes.…
Cryogenic field-effect transistors (FETs) offer great potential for a wide range of applications, the most notable example being classical control electronics for quantum information processors. In the latter context, on-chip FETs with low…
This paper presents a physics-based model for the threshold voltage in bulk MOSFETs valid from room down to cryogenic temperature (4.2 K). The proposed model is derived from Poisson's equation including bandgap widening, intrinsic…
Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77 K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to…
The advancement of quantum technology networks necessitates high-speed, low-thermal load, and minimal-noise communication links between cryogenic and room-temperature components. At the heart of modern telecommunication, lay optical…
This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes.…
Amorphous oxide semiconductors (AOSs) have recently gained attention as a promising channel material of back-end-of-line (BEOL)-compatible transistors for monolithic three-dimensional (3D) integrations. However, the degradation in device…
Narrow-channel accumulated body nMOSFET devices with p-type side-gates surrounding the active area have been electrically characterized between 100 and 400 K with varied side-gate biasing (Vside). The subthreshold slope (SS) and drain…
This brief reports the analytical modeling and measurements of the inflection in the MOSFET transfer characteristics at cryogenic temperatures. Inflection is the inward bending of the drain current versus gate voltage, which reduces the…
In this paper a commercial 28-nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the…
This study optimizes 28 nm planar MOSFET technology to reduce device leakage current and enhance switching speed. The specific aims are to decrease subthreshold swing (S.S.) and mitigate drain induced barrier lowering (DIBL) effect. Silvaco…
We report record performance for black phosphorus p-MOSFETs. The devices have locally patterned back gates and 20-nm-thick HfO2 gate dielectrics. Devices with effective gate length, Leff = 1.0 um display extrinsic transconductance, gm, of…
We fabricate superconducting ion traps with niobium and niobium nitride and trap single 88Sr ions at cryogenic temperatures. The superconducting transition is verified and characterized by measuring the resistance and critical current using…
We present a compact model for Tunnel Field Effect Transistors (TFET), that captures sev- eral non-idealities such as the Trap Assisted Tunneling (TAT) originating from interface traps (Dit), along with Verilog-A implementation. We show…
Power dissipation is a great challenge for the continuous scaling down and performance improvement of CMOS technology, due to thermionic current switching limit of conventional MOSFETs. In this work, we show that this problem can be…
Tunnel field effect transistors (TFETs) utilizing semiconductor heterojunctions have shown promise for low energy logic but presently do not display subthreshold swings steeper than the room-temperature thermal limit of 60 mV/decade. These…