English
Related papers

Related papers: Fixed-Posit: A Floating-Point Representation for E…

200 papers

We present an evaluation of 32-bit POSIT arithmetic through its implementation as accelerators on FPGAs and GPUs. POSIT, a floating-point number format, adaptively changes the size of its fractional part. We developed hardware designs for…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-01-26 Naohito Nakasato , Yuki Murakami , Fumiya Kono , Maho Nakata

Memory becomes a limiting factor in contemporary applications, such as analyses of the Webgraph and molecular sequences, when many objects need to be counted simultaneously. Robert Morris [Communications of the ACM, 21:840--842, 1978]…

Data Structures and Algorithms · Computer Science 2009-08-24 Miklos Csuros

Multi-term floating-point addition appears in vector dot-product computations, matrix multiplications, and other forms of floating-point data aggregation. A critical step in multi-term floating point addition is the alignment of fractions…

Hardware Architecture · Computer Science 2024-10-30 Kosmas Alexandridis , Giorgos Dimitrakopoulos

Frugal computing is becoming an important topic for environmental reasons. In this context, several techniques have been proposed to reduce the storage of scientific data by dedicated compression methods specially tailored for arrays of…

Data Structures and Algorithms · Computer Science 2022-03-01 Matthieu Martel

The Graphic Processing Unit (GPU) has evolved into a powerful and flexible processor. The latest graphic processors provide fully programmable vertex and pixel processing units that support vector operations up to single floating-point…

Hardware Architecture · Computer Science 2007-05-23 Guillaume Da Graçca , David Defour

When quantizing neural networks for efficient inference, low-bit integers are the go-to format for efficiency. However, low-bit floating point numbers have an extra degree of freedom, assigning some bits to work on an exponential scale…

Machine Learning · Computer Science 2024-02-26 Andrey Kuzmin , Mart Van Baalen , Yuwei Ren , Markus Nagel , Jorn Peters , Tijmen Blankevoort

The IEEE 754 floating-point standard is the bedrock of modern computing, but its structural requirements -- a hidden leading bit, Base-2 bit-level normalization, and Sign-Magnitude encoding -- impose significant silicon area and power…

Hardware Architecture · Computer Science 2026-03-11 Keita Morisaki

Incorporating geometric invariance into neural networks enhances parameter efficiency but typically increases computational costs. This paper introduces new equivariant neural networks that preserve symmetry while maintaining a comparable…

Computer Vision and Pattern Recognition · Computer Science 2025-06-25 Georg Bökman , David Nordström , Fredrik Kahl

In todays world, high-power computing applications such as image processing, digital signal processing, graphics, and robotics require enormous computing power. These applications use matrix operations, especially matrix multiplication.…

Hardware Architecture · Computer Science 2019-10-29 Arish S , R. K. Sharma

We propose a novel floating-point encoding scheme that builds on prior work involving fixed-point encodings. We encode floating-point numbers using Two's Complement fixed-point mantissas and Two's Complement integral exponents. We used our…

Advanced driver-assistance systems (ADAS) require neural compute engines that deliver low-latency inference under strict power and area constraints. Posit arithmetic is attractive for such accelerators because it provides high numerical…

Hardware Architecture · Computer Science 2026-05-11 Mukul Lokhande , Ratko Pilipovic , Omkar Kokane , Adam Teman , Santosh Kumar Vishvakarma

Edge-AI applications still face considerable challenges in enhancing computational efficiency in resource-constrained environments. This work presents RAMAN, a resource-efficient and approximate posit(8,2)-based Multiply-Accumulate (MAC)…

Hardware Architecture · Computer Science 2025-10-28 Mohd Faisal Khan , Mukul Lokhande , Santosh Kumar Vishvakarma

Multiplication is a core operation in modern neural network (NN) computations, contributing significantly to energy consumption. The linear-complexity multiplication (L-Mul) algorithm is specifically proposed as an approximate…

Hardware Architecture · Computer Science 2024-12-30 Ruiqi Chen , Yangxintong Lyu , Han Bao , Bruno da Silva

Deep neural networks have enabled progress in a wide variety of applications. Growing the size of the neural network typically results in improved accuracy. As model sizes grow, the memory and compute requirements for training these models…

Reduced precision computation for deep neural networks is one of the key areas addressing the widening compute gap driven by an exponential growth in model size. In recent years, deep learning training has largely migrated to 16-bit…

Machine Learning · Computer Science 2019-05-30 Naveen Mellempudi , Sudarshan Srinivasan , Dipankar Das , Bharat Kaul

As IoT and edge inference proliferate,there is a growing need to simultaneously optimize area and delay in lookup-table (LUT)-based multipliers that implement large numbers of low-bitwidth operations in parallel. This paper proposes a…

Hardware Architecture · Computer Science 2025-10-27 Misaki Kida , Shimpei Sato

The takum machine number format has been recently proposed as an enhancement over the posit number format, which is considered a promising alternative to the IEEE 754 floating-point standard. Takums retain the useful posit properties, but…

Hardware Architecture · Computer Science 2025-11-27 Laslo Hunhold

Our work presents a new iterative scheme to approximate the fixed points of nonexpansive mapping. The proposed algorithm is constructed to enhance convergence efficiency while preserving theoretical robustness. Under appropriate assumptions…

Functional Analysis · Mathematics 2026-01-12 Nida Izhar Mallick , Izhar Uddin

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two…

Hardware Architecture · Computer Science 2025-10-28 L. Hemanth Krishna , Srinivasu Bodapati , Sreehari Veeramachaneni , BhaskaraRao Jammu , Noor Mahammad Sk

When training deep neural networks, keeping all tensors in high precision (e.g., 32-bit or even 16-bit floats) is often wasteful. However, keeping all tensors in low precision (e.g., 8-bit floats) can lead to unacceptable accuracy loss.…

Machine Learning · Computer Science 2023-06-26 Wonyeol Lee , Rahul Sharma , Alex Aiken
‹ Prev 1 3 4 5 6 7 10 Next ›