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Runahead execution is a technique to mask memory latency caused by irregular memory accesses. By pre-executing the application code during occurrences of long-latency operations and prefetching anticipated cache-missed data into the cache…

Hardware Architecture · Computer Science 2025-04-03 Dean You , Jieyu Jiang , Xiaoxuan Wang , Yushu Du , Zhihang Tan , Wenbo Xu , Hui Wang , Jiapeng Guan , Zhenyuan Wang , Ran Wei , Shuai Zhao , Zhe Jiang

Numerous optical circuit switched data center networks have been proposed over the past decade for higher capacity, though commercial adoption of these architectures have been minimal so far. One major challenge commonly facing these…

Networking and Internet Architecture · Computer Science 2020-02-04 Min Yee Teh , Shizhen Zhao , Keren Bergman

Using multiple datacenters allows for higher availability, load balancing and reduced latency to customers of cloud services. To distribute multiple copies of data, cloud providers depend on inter-datacenter WANs that ought to be used…

Networking and Internet Architecture · Computer Science 2018-04-30 Mohammad Noormohammadpour , Cauligi S. Raghavendra , Sriram Rao , Srikanth Kandula

Hardware and OS mechanisms for memory tiering are widely deployed, yet datacenters still overprovision DRAM. The root cause is hotness fragmentation: allocators place objects by size rather than access pattern, so hot and cold objects…

Operating Systems · Computer Science 2026-03-03 Vinay Banakar , Suli Yang , Kan Wu , Andrea C. Arpaci-Dusseau , Remzi H. Arpaci-Dusseau , Kimberly Keeton

Processing-in-memory (PIM) architectures bring computation closer to data, reducing the processor-memory transfer bottleneck in traditional processor-centric designs. Novel hardware solutions, such as UPMEM's in-memory processing…

Emerging Technologies · Computer Science 2026-04-10 Peterson Yuhala , Mpoki Mwaisela , Pascal Felber , Valerio Schiavoni

Prefix caching is crucial to accelerate multi-turn interactions and requests with shared prefixes. At the cluster level, existing prefix caching systems are tightly coupled with request scheduling to optimize cache efficiency and…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-08-26 Bingyang Wu , Zili Zhang , Yinmin Zhong , Guanzhe Huang , Yibo Zhu , Xuanzhe Liu , Xin Jin

This paper introduces Dodoor, an efficient randomized decentralized scheduler designed for task scheduling in modern data centers. Dodoor leverages advanced research on the weighted balls-into-bins model with b-batched setting. Unlike other…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-16 Wei Da , Evangelia Kalyvianaki

Modern high-performance architectures employ large last-level caches (LLCs). While large LLCs can reduce average memory access latency for workloads with a high degree of locality, they can also increase latency for workloads with irregular…

Hardware Architecture · Computer Science 2025-11-26 Hoa Nguyen , Pongstorn Maidee , Jason Lowe-Power , Alireza Kaviani

Modern embedded systems are evolving toward complex, heterogeneous architectures to accommodate increasingly demanding applications. Driven by SWAP-C constraints, this shift has led to consolidating multiple systems onto single hardware…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-01-28 Diogo Costa , Gonçalo Moreira , Afonso Oliveira , José Martins , Sandro Pinto

Resource disaggregation offers a cost effective solution to resource scaling, utilization, and failure-handling in data centers by physically separating hardware devices in a server. Servers are architected as pools of processor, memory,…

Hardware Architecture · Computer Science 2023-01-25 Christina Giannoula , Kailong Huang , Jonathan Tang , Nectarios Koziris , Georgios Goumas , Zeshan Chishti , Nandita Vijaykumar

Mobile Edge Computing (MEC) has been gaining significant interest from first responders and tactical teams, primarily because they can employ handheld mobile devices to form a computing cluster (for computing tasks like face/scene…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-04-26 S. Bhunia , R. Stoleru , M. Sagor , A. Haroon , A. Altaweel , M. Chao , M. Maurice , R. Blalock

Recent literature including our past work provide analysis and solutions for using (i) erasure coding, (ii) parallelism, or (iii) variable slicing/chunking (i.e., dividing an object of a specific size into a variable number of smaller…

Networking and Internet Architecture · Computer Science 2014-03-21 Guanfeng Liang , Ulas C. Kozat

Modern AI clusters, which host diverse workloads like data pre-processing, training and inference, often store the large-volume data in cloud storage and employ caching frameworks to facilitate remote data access. To avoid code-intrusion…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-06-17 Tianze Wang , Yifei Liu , Chen Chen , Pengfei Zuo , Jiawei Zhang , Qizhen Weng , Yin Chen , Zhenhua Han , Jieru Zhao , Quan Chen , Minyi Guo

The rapid adoption of large language models and multimodal foundation models has made multimodal data preparation pipelines critical AI infrastructure. These pipelines interleave CPU-heavy preprocessing with accelerator-backed (GPU/NPU/TPU)…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-03 Ding Pan , Zhuangzhuang Zhou , Long Qian , Binhang Yuan

The inference of ML models composed of diverse structures, types, and sizes boils down to the execution of different dataflows (i.e. different tiling, ordering, parallelism, and shapes). Using the optimal dataflow for every layer of…

Hardware Architecture · Computer Science 2026-04-07 Jianming Tong , Anirudh Itagi , Prasanth Chatarasi , Tushar Krishna

Transformers have revolutionized AI in natural language processing and computer vision, but their large computation and memory demands pose major challenges for hardware acceleration. In practice, end-to-end throughput is often limited by…

Hardware Architecture · Computer Science 2026-03-20 Qunyou Liu , Marina Zapater , David Atienza

Rowhammer is a critical vulnerability in dynamic random access memory (DRAM) that continues to pose a significant threat to various systems. However, we find that conventional load-based attacks are becoming highly ineffective on the most…

Cryptography and Security · Computer Science 2025-10-21 Weijie Chen , Shan Tang , Yulin Tang , Xiapu Luo , Yinqian Zhang , Weizhong Qiang

The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particular, even state-of-the-art graph prefetchers do not work well…

Hardware Architecture · Computer Science 2023-01-31 Yichen Yang , Jingtao Li , Nishil Talati , Subhankar Pal , Siying Feng , Chaitali Chakrabarti , Trevor Mudge , Ronald Dreslinski

Paxos is a prominent theory of state machine replication. Recent data intensive Systems those implement state machine replication generally require high throughput. Earlier versions of Paxos as few of them are classical Paxos, fast Paxos…

Distributed, Parallel, and Cluster Computing · Computer Science 2014-07-07 Vinit Kumar , Ajay Agarwal

A popular run-time attack technique is to compromise the control-flow integrity of a program by modifying function return addresses on the stack. So far, shadow stacks have proven to be essential for comprehensively preventing return…

Cryptography and Security · Computer Science 2020-10-16 Hans Liljestrand , Thomas Nyman , Lachlan J. Gunn , Jan-Erik Ekberg , N. Asokan
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