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Vision Transformers (ViTs) have achieved significant success in computer vision. However, their intensive computations and massive memory footprint challenge ViTs' deployment on embedded devices, calling for efficient ViTs. Among them,…

Hardware Architecture · Computer Science 2024-04-01 Haikuo Shao , Huihong Shi , Wendong Mao , Zhongfeng Wang

This paper presents GraphAGILE, a domain-specific FPGA-based overlay accelerator for graph neural network (GNN) inference. GraphAGILE consists of (1) \emph{a novel unified architecture design} with an \emph{instruction set}, and (2) \emph{a…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-04-25 Bingyi Zhang , Hanqing Zeng , Viktor Prasanna

We present a compilation flow for the generation of CNN inference accelerators on FPGAs. The flow translates a frozen model into OpenCL kernels with the TVM compiler and uses the Intel OpenCL SDK to compile to an FPGA bitstream. We improve…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-03-09 Seung-Hun Chung , Tarek S. Abdelrahman

Emulating chip functionality before silicon production is crucial, especially with the increasing prevalence of RISC-V-based designs. FPGAs are promising candidates for such purposes due to their high-speed and reconfigurable architecture.…

Hardware Architecture · Computer Science 2024-02-06 Elias Perdomo , Alexander Kropotov , Francelly Cano , Syed Zafar , Teresa Cervero , Xavier Martorell , Behzad Salami

The continuous growth of big data applications with high computational and scalability demands has resulted in increasing popularity of cloud computing. Optimizing the performance and power consumption of cloud resources is therefore…

Hardware Architecture · Computer Science 2019-10-30 Sahand Salamat , Behnam Khaleghi , Mohsen Imani , Tajana Rosing

Modern large language models (LLMs) increasingly depends on efficient long-context processing and generation mechanisms, including sparse attention, retrieval-augmented generation (RAG), and compressed contextual memory, to support complex…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-05-12 Zifan He , Rui Ma , Yizhou Sun , Jason Cong

The Cerebras Wafer Scale Engine (WSE) is an accelerator that combines hundreds of thousands of AI-cores onto a single chip. Whilst this technology has been designed for machine learning workloads, the significant amount of available raw…

Distributed, Parallel, and Cluster Computing · Computer Science 2022-10-11 Nick Brown , Brandon Echols , Justs Zarins , Tobias Grosser

Fast and accurate climate simulations and weather predictions are critical for understanding and preparing for the impact of climate change. Real-world weather and climate modeling consist of complex compound stencil kernels that do not…

Field-programmable gate arrays (FPGAs) provide an opportunity to co-design applications with hardware accelerators, yet they remain difficult to program. High-level synthesis (HLS) tools promise to raise the level of abstraction by…

Programming Languages · Computer Science 2021-11-17 Rachit Nigam , Sachille Atapattu , Samuel Thomas , Zhijing Li , Theodore Bauer , Yuwei Ye , Apurva Koti , Adrian Sampson , Zhiru Zhang

We implement a specialized version of our SpeckleNN model for real-time speckle pattern classification in X-ray Single-Particle Imaging (SPI) using the SLAC Neural Network Library (SNL) on an FPGA. This hardware is optimized for inference…

Instrumentation and Detectors · Physics 2025-02-28 Abhilasha Dave , Cong Wang , James Russell , Ryan Herbst , Jana Thayer

In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by…

Hardware Architecture · Computer Science 2015-03-13 Jorge Luiz e Silva , Joelmir Jose Lopes , Bruno de Abreu Silva , Antonio Carlos Fernandes da Silva

Edge AI deployment faces critical challenges balancing computational performance, energy efficiency, and resource constraints. This paper presents FPGA-accelerated RISC-V instruction set architecture (ISA) extensions for efficient neural…

Hardware Architecture · Computer Science 2025-11-11 Arya Parameshwara , Santosh Hanamappa Mokashi

Point cloud processing is a computational bottleneck in autonomous driving systems, especially for real-time applications, while energy efficiency remains a critical system constraint. This work presents FPPS, an FPGA-accelerated point…

Hardware Architecture · Computer Science 2026-03-02 Xiaofeng Zhou , Linfeng Du , Hanwei Fan , Wei Zhang

The growing adoption of Deep Learning (DL) applications in the Internet of Things has increased the demand for energy-efficient accelerators. Field Programmable Gate Arrays (FPGAs) offer a promising platform for such acceleration due to…

Hardware Architecture · Computer Science 2025-04-15 Chao Qian

The growing demand for deploying Small Language Models (SLMs) on edge devices, including laptops, smartphones, and embedded platforms, has exposed fundamental inefficiencies in existing accelerators. While GPUs handle prefill workloads…

Hardware Architecture · Computer Science 2026-04-14 Jinane Bazzi , Mariam Rakka , Fadi Kurdahi , Mohammed E. Fouda , Ahmed Eltawil

A variety of computing platform like Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU) and multicore Central Processing Unit (CPU) in data centers are suitable for acceleration of data-intensive workloads. Especially,…

Hardware Architecture · Computer Science 2023-11-21 Rourab Paul , Marco Danelutto

Embedded Field-Programmable Gate Arrays (eFPGAs) allow for the design of hardware accelerators of edge Machine Learning (ML) applications at a lower power budget compared with traditional FPGA platforms. However, the limited eFPGA logic and…

Hardware Architecture · Computer Science 2025-02-13 Tousif Rahman , Gang Mao , Bob Pattison , Sidharth Maheshwari , Marcos Sartori , Adrian Wheeldon , Rishad Shafik , Alex Yakovlev

Many aerospace and automotive applications use FPGAs in their designs due to their low power and reconfigurability requirements. Meanwhile, such applications also pose a high standard on system reliability, which makes the early-stage…

Hardware Architecture · Computer Science 2023-03-23 Eduardo Rhod , Behnam Ghavami , Zhenman Fang , Lesley Shannon

The rapid updates in error-resilient applications along with their quest for high throughput have motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies that proposed imprecise functional…

Hardware Architecture · Computer Science 2022-06-29 Zahra Ebrahimi , Muhammad Zaid , Mark Wijtvliet , Akash Kumar

Designing hardware is a time-consuming and complex process. Realization of both, embedded and high-performance applications can benefit from a design process on a higher level of abstraction. This helps to reduce development time and allows…

Software Engineering · Computer Science 2015-09-01 Franz Richter-Gottfried , Alexander Ditter , Dietmar Fey