Related papers: A high resolution multi-phase clock Time-Digital C…

We present the design of a new $\mu$TCA-based waveform digitizer, which will be deployed in the Muon g-2 experiment at Fermilab and will allow our pileup identification requirement to be met. This digitizer features five independent…

In next generation wireless communication system, wireless transceivers should be able to handle wideband input signals compromising of multiple communication standards.Such multi-standard wireless communication receivers (MWCRs) need…

A new Digital Pulse Processing (DPP) module has been developed, based on a domino ring sampler version 4 chip (DRS4), with good time resolution for LaBr3 detectors, and different digital timing analysis methods for processing the raw…

The field of photonic integrated circuits has witnessed significant progress in recent years, with a growing demand for devices that offer high-performance reconfigurability. Due to the inability of conventional tunable directional couplers…

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density…

Time-of-flight measurement is an important advancement in PET scanners to improve image reconstruction with a lower delivered radiation dose. This article describes the monolithic ASIC for the TT-PET project, a novel idea for a…

We describe a many-channel experiment control system based on a field-programmable gate array (FPGA). The system has 16 bit resolution on 10 analog 100 MS/s input channels, 14 analog 100 MS/s output channels, 16 slow analog input and output…

SiGe BiCMOS technology can be used to produce ultra-fast, low-power silicon pixel sensors that provide state-of-the-art time resolution even without an internal gain mechanism. The development of such sensors requires the identification of…

For the advancement of the understanding of timing systematics in pixelized readout chips and for the benefit of future fast timing detectors to aid 4D tracking technology in the HL-LHC, we have performed detailed studies of the timing…

We present a compact FPGA-based pulse sequencer and radio-frequency (RF) generator suitable for experiments with cold trapped ions and atoms. The unit is capable of outputting a pulse sequence with at least 32 TTL channels with a timing…

We construct a terahertz time-domain spectrometer (THz-TDS) system based on photoconductive antenna (PCA). A 800 nm Ti sapphire femtosecond laser with 80 MHz repetition rate provides the pump and probe laser pulse, which has a 45 fs pulse…

In recent years Gas Electron Multipliers have proven to be reliable amplification stages at high beam rates, and can be used also in Time Projection Chambers. Our group developed a 1 dm$^3$ active volume double-GEM TPC, with spatial…

The prototype of time digitizing system for the upgrade of BESIII endcap TOF (ETOF) is introduced in this paper. The ETOF readout electronics has a formation of distributed architecture that hit signal from multi-gap resistive plate chamber…

We have developed a means for accurate time transfer using optical fibers and aim at the synchronization of clocks located at different places on an institute campus with an overall uncertainty of 100 ps or better. Such an installation…

Real-time frequency readout of time-dependent pulsed signals with a high sensitivity are key elements in many applications using atomic devices, such as FID atomic magnetometers. In this paper, we propose a frequency measurement algorithm…

The SAMpler for PICosecond time (SAMPIC) chip has been designed by a collaboration including CEA/IRFU/SEDI, Saclay and CNRS/LAL/SERDI, Orsay. It benefits from both the quick response of a time to digital converter and the versatility of a…

The signal digitization for CROSS, a bolometric experiment for the search of neutrinoless double beta decay at LSC - Canfranc Underground Laboratory, will be based on a custom solution comprised of an analog-to-digital board interfaced to…

Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of…

We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low-Power…

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators.…