Related papers: C for a tiny system
The paper deals with orthogonal space-time block coded MC-CDMA systems in outdoor realistic downlink scenarios with up to two transmit and receive antennas. Assuming no channel state information at the transmitter, we compare several linear…
Embedded and IoT devices, largely powered by microcontroller units (MCUs), could be made more intelligent by leveraging on-device deep learning. One of the main challenges of neural network inference on an MCU is the extremely limited…
Compute-in-memory (CiM) architectures promise significant improvements in energy efficiency and throughput for deep neural network acceleration by alleviating the von Neumann bottleneck. However, their reliance on emerging non-volatile…
This paper explores the possibilities of using a computing methodology --hardware and software-- that employs technology other than binary. I refer to this as "supra - binary" computing. Software constructs that use more than binary…
Resource constraints in smart devices demand an efficient cryptosystem that allows for low power and memory consumption. This has led to popularity of comparatively efficient Elliptic curve cryptog-raphy (ECC). Prior to this paper, much of…
We present enhancements to SDPB, an open source, parallelized, arbitrary precision semidefinite program solver designed for the conformal bootstrap. The main enhancement is significantly improved performance and scalability using the…
Many small-scale software systems, that is, with limited codebase or binary size, are widely used in everyday tasks, yet their configurability remains largely unexplored. At the same time, studies on modern software systems show a trend…
The reliability of memory devices is affected by radiation induced soft errors. Multiple cell upsets (MCUs) caused by radiation corrupt data stored in multiple cells within memories. Error correction codes (ECCs) are typically used to…
Decreasing hardware feature sizes and increasing heterogeneity in multicore hardware require software that can adapt to these platforms' properties. We implemented ROMAIN, an OS service providing redundant multithreading on top of the…
Spatially coupled low-density parity-check (SC-LDPC) codes can achieve the channel capacity under low-complexity belief propagation (BP) decoding, however, there is a non-negligible rate-loss because of termination effects for practical…
Staircase codes (SCCs) are typically decoded using iterative bounded-distance decoding (BDD) and hard decisions. In this paper, a novel decoding algorithm is proposed, which partially uses soft information from the channel. The proposed…
Model-predictive control (MPC) is a state-of-the-art control method for constrained robotic systems, yet deployment on resource-limited hardware remains difficult. This challenge is magnified by expressive conic constraints, which offer…
Quantum error correction is rapidly seeing first experimental implementations, but there is a significant gap between asymptotically optimal error-correcting codes and codes that are experimentally feasible. Quantum LDPC codes range from…
This paper presents the design of CIC filters based on a low-pass filter for reducing the sampling rate, also known as decimation process. The targeted application for the filter is in the analog to digital conversion (ADC).The CIC is…
Probabilistic (p-) bits implemented with low energy barrier nanomagnets (LBMs) have recently gained attention because they can be leveraged to perform some computational tasks very efficiently. Although more error-resilient than Boolean…
Heterogeneous systems appear as a viable design alternative for the dark silicon era. In this paradigm, a processor chip includes several different technological alternatives for implementing a certain logical block (e.g., core, on-chip…
The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom…
For Application Specific Integrated Circuits (ASIC) and System-on-Chip (SOC) designs, Cell - Based Design (CBD) is the most prevalent practice as it guarantees a shorter design cycle, minimizes errors and is easier to maintain. In modern…
Protograph-based low-density parity-check Hadamard codes (PLDPC-HCs) are a new type of ultimate-Shannon-limit-approaching codes. In this paper, we propose a hardware architecture for the PLDPC-HC layered decoders. The decoders consist…
This paper presents a low-power cache architecture based on the series interconnection of conventional 6-transistor static random-access memory (6T SRAM) cells. The proposed approach aims to reduce leakage power in SRAM-based cache memories…