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FPGAs are starting to be enhanced with High Bandwidth Memory (HBM) as a way to reduce the memory bandwidth bottleneck encountered in some applications and to give the FPGA more capacity to deal with application state. However, the…

Hardware Architecture · Computer Science 2020-05-12 Zeke Wang , Hongjing Huang , Jie Zhang , Gustavo Alonso

Developing parallel algorithms efficiently requires careful management of concurrency across diverse hardware architectures. C++ executors provide a standardized interface that simplifies the development process, allowing developers to…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-22 Karame Mohammadiporshokooh , Steven R. Brandt , Hartmut Kaiser

Robust execution environments are important for addressing key challenges in quantum computing, such as application development, portability, and reproducibility, and help unlock the development of modular quantum programs, driving forward…

Quantum Physics · Physics 2025-09-26 Aleksander Wennersteen , Matthieu Moreau , Aurelien Nober , Mourad Beji

The growing disparity between CPU core counts and available memory bandwidth has intensified memory contention in servers. This particularly affects highly parallelizable applications, which must achieve efficient cache utilization to…

Hardware Architecture · Computer Science 2025-03-17 Alessandro Fogli , Bo Zhao , Peter Pietzuch , Jana Giceva

We present a portable platform, called PIC_ENGINE, for accelerating Particle-In-Cell (PIC) codes on heterogeneous many-core architectures such as Graphic Processing Units (GPUs). The aim of this development is efficient simulations on…

Computational Physics · Physics 2016-06-08 F. Hariri , T. M. Tran , A. Jocksch , E. Lanti , J. Progsch , P. Messmer , S. Brunner , G. Gheller , L. Villard

Memory tiering systems seek cost-effective memory scaling by adding multiple tiers of memory. For maximum performance, frequently accessed (hot) data must be placed close to the host in faster tiers and infrequently accessed (cold) data can…

Operating Systems · Computer Science 2025-08-07 Sujay Yadalam , Konstantinos Kanellis , Michael Swift , Shivaram Venkataraman

Field Programmable Gate Arrays (FPGAs) have recently been increasingly used for highly-parallel processing of compute intensive tasks. This paper introduces an FPGA hardware platform architecture that is PC-based, allows for fast…

Hardware Architecture · Computer Science 2007-05-23 Andreas Weisensee , Darran Nathan

High Performance Computing~(HPC) software stacks have become complex, with the dependencies of some applications numbering in the hundreds. Packaging, distributing, and administering software stacks of that scale is a complex undertaking…

Software Engineering · Computer Science 2022-11-14 Farid Zakaria , Thomas R. W. Scogland , Todd Gamblin , Carlos Maltzahn

Exceptions and errors occurring within mission critical applications due to hardware failures have a high cost. With the emerging Next Generation Platforms (NGPs), the rate of hardware failures will likely increase. Therefore, designing our…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-10-22 Nikunj Gupta , Jackson R. Mayo , Adrian S. Lemoine , Hartmut Kaiser

In recent years the computational capacity of single Field Programmable Gate Arrays (FPGA) devices as well as their versatility has increased significantly. Adding to that the High Level Synthesis frameworks allowing to program such…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-07-22 G. Korcyl , P. Korcyl

High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) has recently emerged as a suitable solution to address this…

Hardware Architecture · Computer Science 2023-09-06 Jie Chen , Igor Loi , Eric Flamand , Giuseppe Tagliavini , Luca Benini , Davide Rossi

Research in compute resource management for cloud-native applications is dominated by the problem of setting optimal CPU limits -- a fundamental OS mechanism that strictly restricts a container's CPU usage to its specified CPU-limits .…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-10-23 Chirag Shetty , Sarthak Chakraborty , Hubertus Franke , Larisa Shwartz , Chandra Narayanaswami , Indranil Gupta , Saurabh Jha

The OpenMosix approach is a good solution to build powerful and scalable computing farms. Furthermore an easy management infrastructure is implemented using diskless nodes and network boot procedures. In HENP environment, the choice of…

High Energy Physics - Experiment · Physics 2007-05-23 R. Esposito , P. Mastroserio , G. Tortone , F. M. Taurino

Disaggregated memory is a promising approach that addresses the limitations of traditional memory architectures by enabling memory to be decoupled from compute nodes and shared across a data center. Cloud platforms have deployed such…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-06-21 Nan Ding , Pieter Maris , Hai Ah Nam , Taylor Groves , Muaaz Gul Awan , LeAnn Lindsey , Christopher Daley , Oguz Selvitopi , Leonid Oliker , Nicholas Wright , Samuel Williams

Power consumption is a critical consideration in high performance computing systems and it is becoming the limiting factor to build and operate Petascale and Exascale systems. When studying the power consumption of existing systems running…

Distributed, Parallel, and Cluster Computing · Computer Science 2015-01-27 Radim Vavřík , Antoni Portero , Štěpán Kuchař , Martin Golasowski , Simone Libutti , Giuseppe Massari , William Fornaciari , Vít Vondrák

Let's HPC (www.letshpc.org) is an open-access online platform to supplement conventional classroom oriented High Performance Computing (HPC) and Parallel & Distributed Computing (PDC) education. The web based platform provides online…

Computers and Society · Computer Science 2017-01-24 Akshar Varma , Yashwant Keswani , Yashodhan Bhatnagar , Bhaskar Chaudhury

Applications with low data reuse and frequent irregular memory accesses, such as graph or sparse linear algebra workloads, fail to scale well due to memory bottlenecks and poor core utilization. While prior work with prefetching,…

Hardware Architecture · Computer Science 2023-05-05 Marcelo Orenes-Vera , Esin Tureci , David Wentzlaff , Margaret Martonosi

Heterogeneous computing is one of the most important computational solutions to meet rapidly increasing demands on system performance. It typically allows the main flow of applications to be executed on a CPU while the most computationally…

Software Engineering · Computer Science 2020-12-11 Hugo Andrade , Ola Benderius , Christian Berger , Ivica Crnkovic , Jan Bosch

Processing large-scale graph datasets is computationally intensive and time-consuming. Processor-centric CPU and GPU architectures, commonly used for graph applications, often face bottlenecks caused by extensive data movement between the…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-02-11 Marzieh Barkhordar , Alireza Tabatabaeian , Mohammad Sadrosadati , Christina Giannoula , Juan Gomez Luna , Izzat El Hajj , Onur Mutlu , Alaa R. Alameldeen

Azure Cloud offers a wide range of resources for running HPC workloads, requiring users to configure their deployment by selecting VM types, number of VMs, and processes per VM. Suboptimal decisions may lead to longer execution times or…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-12-04 Marco A. S. Netto , Wolfgang De Savador , Davide Vanzo