Related papers: DMR-based Technique for Fault Tolerant AES S-box A…
This paper considers reliable data transfer in a high-speed network (HSN) in which the per-connection capacity is very large. We focus on sliding window protocols employing selective repeat for reliable data transfer and study two…
Fault-tolerant routing (FTR) in Networks-on-Chip (NoCs) has become a common practice to sustain the performance of multi-core systems with an increasing number of faults on a chip. On the other hand, usage of third-party intellectual…
Safra's distributed termination detection algorithm employs a logical token ring structure within a distributed network; only passive nodes forward the token, and a counter in the token keeps track of the number of sent minus the number of…
This paper studies the massive MIMO full-duplex relaying (MM-FDR), where multiple source-destination pairs communicate simultaneously with the help of a common full-duplex relay equipped with very large antenna arrays. Different from the…
An Adaptive Fault-tolerant Controller procedure for a class of the affine nonlinear system is developed in this paper. This methodology hides both the faults and external disturbances. Compare to the procedure that require separate fault…
This paper presents a systematic approach to detecting High Impedance Faults (HIFs) in medium voltage distribution networks using recurrence plots and machine learning. We first simulate 1150 internal faults, including 300 HIFs, 1000…
In this paper, we assess the security and testability of the state-of-the-art design-for-security (DFS) architectures in the presence of scan-chain locking/obfuscation, a group of solution that has previously proposed to restrict…
Implementations of state-machine replication (SMR) prevalently use the variants of Paxos. Some of the recent variants of Paxos like, Ring Paxos, Multi-Ring Paxos, S-Paxos and HT-Paxos achieve significantly high throughput. However, to meet…
Despite years of intensive research, Byzantine fault-tolerant (BFT) systems have not yet been adopted in practice. This is due to additional cost of BFT in terms of resources, protocol complexity and performance, compared with crash…
Floating point arithmetic is costly on FPGA platforms due to wide datapaths, normalization, and carry propagation, motivating alternative numerical representations that improve throughput and efficiency. This paper presents the Hybrid…
Topological error correction codes are promising candidates to protect quantum computations from the deteriorating effects of noise. While some codes provide high noise thresholds suitable for robust quantum memories, others allow…
We conducted the feasibility analysis of utilizing a highly available multi-stage architecture for TSN switches used for sending high priority, mission-critical traffic within a bounded latency instead of traditional single-stage…
Protection against dc faults is one of the main technical hurdles faced when operating converter-based HVdc systems. Protection becomes even more challenging for multi-terminal dc (MTdc) systems with more than two terminals/converter…
High-level synthesis (HLS) transforms an algorithmic description of hardware from a higher abstraction (e.g., C/C++) into a register-transfer level (RTL) design, offering reduced development time and greater flexibility in design space…
Failure Mode Reasoning (FMR) is a novel approach for analyzing failure in a Safety Instrumented System (SIS). The method uses an automatic analysis of an SIS program to calculate potential failures in parts of the SIS. In this paper we use…
Recent research in consensus has often focussed on protocols for State-Machine-Replication (SMR) that can handle high throughputs. Such state-of-the-art protocols (generally DAG-based) induce undue overhead when the needed throughput is…
In this work, we address reliable communication of low-latency packets in the presence of a full-duplex adversary that is capable of executing a jamming attack while also being able to measure the power levels on various frequency bands.…
AES-128 encryption is theoretically secure but vulnerable in practical deployments due to timing and fault injection attacks on embedded systems. This work presents a lightweight dual-detection framework combining statistical thresholding…
Advanced Encryption Standard (AES) implementations on Field Programmable Gate Arrays (FPGA) commonly focus on maximizing throughput at the cost of utilizing high volumes of FPGA slice logic. High resource usage limits systems' abilities to…
This article presents a depth-first search (DFS)-based algorithm for evaluating sensitivity gradients in the topology optimization of soft materials exhibiting complex deformation behavior. The algorithm is formulated using a time-dependent…