Related papers: Characterization of a gigabit transceiver for the …

This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR has four upstream receiver…

We present two prototypes of a gigabit transceiver ASIC, GBCR1 and GBCR2, both designed in a 65-nm CMOS technology for the ATLAS Inner Tracker Pixel Detector readout upgrade. The first prototype, GBCR1, has four upstream receiver channels…

This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for the HL-LHC upgrade of the ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, and GBCR3) have been designed in the…

We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6…

For the High Luminosity upgrade of the Large Hadron Collider the current ATLAS Inner Detector will be replaced by an all-silicon Inner Tracker. The pixel detector will consist of five barrel layers and a number of rings, resulting in about…

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS…

This paper presents the design and characterisation of a front-end prototype ASIC for the ATLAS High Granularity Timing Detector, which is planned for the High-Luminosity phase of the LHC. This prototype, called ALTIROC1, consists of a…

This paper presents experimental and simulation data to characterize the Ring Oscillators (RO) produced in 65-nm CMOS technology for the next promising generation of readout chips for the pixel detector in the Inner Tracker (ITk) at the…

This contribution introduces a novel test system developed to evaluate the signal transmission quality in high-speed data links for the 2026 Inner Tracker (ITk) upgrade of the ATLAS experiment. Using an FPGA-based data acquisition (DAQ)…

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital…

The ALICE collaboration is preparing an upgrade of the three innermost layers of the current Inner Tracking System (ITS) during the next LHC long shutdown (LS3). The new ITS detector will use wafer-scale (up to \SI{27}{cm} in length)…

We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the…

The SemiConductor Tracker (SCT) together with the Pixel detector and the Transition Radiation Tracker (TRT) form the central tracking system of the ATLAS experiment at the LHC. It consists of single-sided microstrip silicon sensors, which…

We introduce the broadband reconfigurable intelligent surface (RIS) channel (BRISC) dataset. The dataset comprises measurements of channel state information (CSI) collected at 5.53 GHz using a 256-element RIS with binary states. In the…

We present the design and characterization of TIGER (Turin Integrated Gem Electronics for Readout), a 64-channel ASIC developed for the readout of the CGEM (Cylindrical Gas Electron Multiplier) detector, the proposed inner tracker for the…

We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-{\mu}m silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first…

The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an…

The planned HL-LHC (High Luminosity LHC) in 2025 is being designed to maximise the physics potential through a sizable increase in the luminosity up to 6*10^34 cm^-2 s^-1. A consequence of this increased luminosity is the expected radiation…

During the ATLAS phase II upgrade, the tracking system of the ATLAS experiment will be replaced by an all-silicon detector called the inner tracker (ITK) with a pixel detector as the most inner part. The monitoring data of the new system…

Following the Phase-II upgrade during Long Shutdown (LS3), the LHC aims to reach a peak instantaneous luminosity of $7.5\times 10^{34}$cm$^{-2}$s$^{-1}$, which corresponds to an average of around 200 inelastic proton-proton collisions per…