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Modern high-performance architectures employ large last-level caches (LLCs). While large LLCs can reduce average memory access latency for workloads with a high degree of locality, they can also increase latency for workloads with irregular…

Hardware Architecture · Computer Science 2025-11-26 Hoa Nguyen , Pongstorn Maidee , Jason Lowe-Power , Alireza Kaviani

Data prefetching is important for storage system optimization and access performance improvement. Traditional prefetchers work well for mining access patterns of sequential logical block address (LBA) but cannot handle complex…

Operating Systems · Computer Science 2023-10-12 Yiyuan Yang , Rongshang Li , Qiquan Shi , Xijun Li , Gang Hu , Xing Li , Mingxuan Yuan

High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is…

Hardware Architecture · Computer Science 2021-03-30 Majid Jalili , Mattan Erez

This paper describes the application of a high-level language and method in developing simpler specifications of more complex variants of the Paxos algorithm for distributed consensus. The specifications are for Multi-Paxos with preemption,…

Distributed, Parallel, and Cluster Computing · Computer Science 2020-12-25 Yanhong A. Liu , Saksham Chand , Scott D. Stoller

The performance of large-scale computing systems often critically depends on high-performance communication networks. Dynamically reconfigurable topologies, e.g., based on optical circuit switches, are emerging as an innovative new…

Networking and Internet Architecture · Computer Science 2022-12-29 Vamsi Addanki , Chen Avin , Stefan Schmid

Data prefetching--loading data into the cache before it is requested--is essential for reducing I/O overhead and improving database performance. While traditional prefetchers focus on sequential patterns, recent learning-based approaches,…

Databases · Computer Science 2025-10-14 Farzaneh Zirak , Farhana Choudhury , Renata Borovica-Gajic

FPGAs are well-suited for dataflow architectures that process data in a streaming or pipelined manner, thus satisfying the high computational and communication demands of emerging applications. However, manually implementing an efficient…

Hardware Architecture · Computer Science 2026-04-15 Weichuang Zhang , Yiquan Wang , Xinzhou Zhang , Chi Zhang , Yu Feng , Xiaofeng Hou , Chao Li , Jieru Zhao , Minyi Guo

Recently several CSMA algorithms based on the Glauber dynamics model have been proposed for multihop wireless scheduling, as viable solutions to achieve the throughput optimality, yet are simple to implement. However, their delay…

Networking and Internet Architecture · Computer Science 2013-08-01 Jaewook Kwak , Chul-Ho Lee , Do Young Eun

With ever-increasing main memory stall times, we need novel techniques to reduce effective memory access latencies. Prefetching has been shown to be an effective solution, especially with contiguous data structures that follow the…

Hardware Architecture · Computer Science 2025-05-29 Nikola Vuk Maruszewski

Transformer-based models can perform complicated reasoning by generating reasoning paths token by token. While effective, this approach often requires generating thousands of tokens to solve a single problem, which can be slow and…

Machine Learning · Computer Science 2026-05-05 Jiayu Liu , Zhenya Huang , Xuan Yang , Tianyun Ji , Anya Sims , Hao Xu , Enhong Chen , Yee Whye Teh , Ning Miao

Distributed filesystem metadata updates are typically synchronous. This creates inherent challenges for access efficiency, load balancing, and directory contention, especially under dynamic and skewed workloads. This paper argues that…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-01-01 Jingwei Xu , Mingkai Dong , Qiulin Tian , Ziyi Tian , Tong Xin , Haibo Chen

The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particular, even state-of-the-art graph prefetchers do not work well…

Hardware Architecture · Computer Science 2023-01-31 Yichen Yang , Jingtao Li , Nishil Talati , Subhankar Pal , Siying Feng , Chaitali Chakrabarti , Trevor Mudge , Ronald Dreslinski

Memory performance is a bottleneck in graph analytics acceleration. Existing Machine Learning (ML) prefetchers struggle with phase transitions and irregular memory accesses in graph processing. We propose MPGraph, an ML-based Prefetcher for…

Machine Learning · Computer Science 2023-09-26 Pengmiao Zhang , Rajgopal Kannan , Viktor K. Prasanna

We present a novel method for computing reachability probabilities of parametric discrete-time Markov chains whose transition probabilities are fractions of polynomials over a set of parameters. Our algorithm is based on two key…

Software Engineering · Computer Science 2014-03-28 Nils Jansen , Florian Corzilius , Matthias Volk , Ralf Wimmer , Erika Ábrahám , Joost-Pieter Katoen , Bernd Becker

There is a growing need for distributed graph processing systems that are capable of gracefully scaling to very large graph datasets. Unfortunately, this challenge has not been easily met due to the intense memory pressure imposed by…

Databases · Computer Science 2014-07-03 Yingyi Bu , Vinayak Borkar , Jianfeng Jia , Michael J. Carey , Tyson Condie

Cache prefetcher greatly eliminates compulsory cache misses, by fetching data from slower memory to faster cache before it is actually required by processors. Sophisticated prefetchers predict next use cache line by repeating program's…

Hardware Architecture · Computer Science 2017-12-05 Haoyuan Wang , Zhiwei Luo

We propose a generic Markov Chain Monte Carlo (MCMC) algorithm to speed up computations for datasets with many observations. A key feature of our approach is the use of the highly efficient difference estimator from the survey sampling…

Methodology · Statistics 2017-08-03 Matias Quiroz , Mattias Villani , Robert Kohn

To improve the application-level communication performance, scheduling of coflows, a collection of parallel flows sharing the same objective, is prevalent in modern data center networks (DCNs). Meanwhile, a hybrid-switched DCN design…

Networking and Internet Architecture · Computer Science 2023-06-19 Xin Wang , Hong Shen , Hui Tian

Switching, routing, and security functions are the backbone of packet processing networks. Fast and efficient processing of packets requires maintaining the state of a large number of transient network connections. In particular, modern…

Networking and Internet Architecture · Computer Science 2023-05-05 Luke McHale , Paul V Gratz , Alex Sprintson

Packet classification is a vital and complicated task as the processing of packets should be done at a specified line speed. In order to classify a packet as belonging to a particular flow or set of flows, network nodes must perform a…

Networking and Internet Architecture · Computer Science 2014-04-08 Pallavi. V. S , Dr. Rukmani Devi. D
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