Related papers: A Multi-Layer SEU Mitigation Strategy to Improve F…

This paper reports on the development of a resource-efficient FPGA-based neural network regression model for potential applications in the future hardware muon trigger system of the ATLAS experiment at the Large Hadron Collider (LHC).…

We propose a new fixed latency scheme for Xilinx gigabit transceivers that will be used in the upgrade of the ATLAS forward muon spectrometer at the Large Hadron Collider. The fixed latency scheme is implemented in a 4.8 Gbps link between a…

The High-Luminosity LHC will provide the unique opportunity to explore the nature of physics beyond the Standard Model of strong and electroweak interactions. Highly selective first level triggers are essential for the physics programme of…

Digital off-detector electronics in trigger and data acquisition systems of High-Energy Physics experiments is often implemented by means of SRAM-based FPGAs, which make it possible to achieve reconfigurable, real-time processing and…

SRAM-based FPGAs are increasingly popular in the aerospace industry due to their field programmability and low cost. However, they suffer from cosmic radiation induced Single Event Upsets (SEUs). In safety-critical applications, the…

Neural Networks (NNs) are increasingly used in the last decade in several demanding applications, such as object detection and classification, autonomous driving, etc. Among different computing platforms for implementing NNs, FPGAs have…

The AMD UltraScale+ XCZU9EG device is a Multi-Processor System-on-Chip (MPSoC) with embedded Programmable Logic (PL) that excels in many Edge (e.g., automotive or avionics) and Cloud (e.g., data centres) terrestrial applications. However,…

High-speed serial links implemented in SRAM-based FPGAs have been extensively used in the trigger and data acquisition systems of High Energy Physics experiments. Usually, their application has been restricted to off-detector, mostly due…

Dynamic partial reconfiguration enables multi-tenancy in cloud-based FPGAs, which presents security challenges for tenants, IPs, and data. Malicious users can exploit FPGAs for remote side-channel attacks (SCAs), and shared on-chip…

After successfully completing Phase I upgrades during LHC Long Shutdown 2, the ATLAS detector is back in operation with several upgrades implemented. The most important and challenging upgrade is in the Muon Spectrometer, where the two…

For Run 3 (from 2021), the LHC will undergo a significant increase in instantaneous luminosity to 1.5 times its current value which will lead to larger collected statistics and an enhanced sensitivity to new physics. The Phase-1 upgrade of…

We report on the construction and initial performance studies of two micromegas detector quadruplets with an area of 0.5 m$^2$. They serve as prototypes for the planned upgrade project of the ATLAS muon system. Their design is based on the…

An extensive system test of the ATLAS muon spectrometer has been performed in the H8 beam line at the CERN SPS during the last four years. This spectrometer will use pressurized Monitored Drift Tube (MDT) chambers and Cathode Strip Chambers…

The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an…

The demand for more developed and agile urban taxi drones is increasing rapidly nowadays to sustain crowded cities and their traffic issues. The critical factor for spreading such technology could be related to the safety criteria that must…

The Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC makes use of Resistive Plate Chamber (RPC) detectors. The on-detector trigger electronics modules are able to identify muons with predefined transverse momentum values (pT) by…

The ATLAS experiment at the Large Hadron Collider (LHC) at CERN is currently waiting to record the first collision data in spring 2009. Its muon spectrometer is designed to achieve a momentum resolution of 10% pT(mu) = 1 TeV/c. The…

We propose FPGA-Patch, the first-of-its-kind defense that leverages automated program repair concepts to thwart power side-channel attacks on cloud FPGAs. FPGA-Patch generates isofunctional variants of the target hardware by injecting…

SRAM-based FPGAs are popular in the aerospace industry for their field programmability and low cost. However, they suffer from cosmic radiation-induced Single Event Upsets (SEUs). Triple Modular Redundancy (TMR) is a well-known technique to…

This paper explores advances in reconfiguration properties of SRAM-based FPGAs, namely Partial Dynamic Reconfiguration, to improve the resilience of critical systems that take advantage of this technology. Commercial of-the-shelf…