Related papers: ERSFQ 8-bit Parallel Arithmetic Logic Unit
Digital single-flux quantum (SFQ) technology promises to meet the demands of ultra low power and high speed computing needed for future exascale supercomputing platforms. However, clocking SFQ logic circuits remains a challenge due to the…
Quantum computing using superconducting circuits underwent rapid development in the last decade. This field has propelled from quantum manipulation of single two-level systems to complex designs employing multiple coupled qubits allowing…
In the recent era, Reversible computing is a growing field having applications in nanotechnology, optical information processing, quantum networks etc. In this paper, the authors show the design of a cost effective reversible programmable…
Packages capable of supporting large arrays of high-coherence superconducting qubits are vital for the realisation of fault-tolerant quantum computers and the necessary high-throughput metrology required to optimise fabrication and…
Analog computing has been recently revived due to its potential for energy-efficient and highly parallel computations. In this two-part paper, we explore analog computers that linearly process microwave signals, named microwave linear…
Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, these models often struggle with…
Exponential Linear Units (ELUs) are a useful rectifier for constructing deep learning architectures, as they may speed up and otherwise improve learning by virtue of not have vanishing gradients and by having mean activations near zero.…
APEmille is a SIMD parallel processor under development at the Italian National Institute for Nuclear Physics (INFN). APEmille is very well suited for Lattice QCD applications, both for its hardware characteristics and for its software and…
Designing analog circuits from performance specifications is a complex, multi-stage process encompassing topology selection, parameter inference, and layout feasibility. We introduce FALCON, a unified machine learning framework that enables…
The presented paper introduces a design for a phase-locked loop (PLL) that is utilized in frequency synthesis and modulation-demodulation within communication systems and in VLSI applications. The CMOS PLL is designed using 180 nm…
In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences…
Noisy intermediate-scale quantum (NISQ) devices seek to achieve quantum advantage over classical systems without the use of full quantum error correction. We propose a NISQ processor architecture using a qubit `pipeline' in which all…
Adiabatic quantum-flux-parametron (AQFP) logic is a proven energy-efficient superconductor technology for various applications. To address the scalability challenges, we investigated AQFP shift registers with the AQFP footprint area reduced…
Continuous developments in Additive Manufacturing (AM) technologies are opening opportunities in novel machining, and improving design alternatives for modern particle accelerator components. One of the most critical, complex, and delicate…
The AIDA-2020 Trigger Logic Unit (TLU) has been designed to be a flexible and easily configurable unit to provide trigger and control signals to devices employed during test beams, integrating them with the beam telescope. The most recent…
In many physical approaches to quantum computation, error-correction schemes assume the ability to form two-dimensional qubit arrays with nearest-neighbor couplings and parallel operations at multiple qubit sites. While semiconductor spin…
Analog In-Memory Computing (AIMC) is an emerging technology for fast and energy-efficient Deep Learning (DL) inference. However, a certain amount of digital post-processing is required to deal with circuit mismatches and non-idealities…
We describe the calibration and imaging heuristics developed and deployed in the ALMA interferometric data processing pipeline, as of ALMA Cycle 9. The pipeline software framework is written in Python, with each data reduction stage layered…
We present theoretical schemes for performing high-fidelity one- and two-qubit pulsed gates for a superconducting flux qubit. The "IBM qubit" consists of three Josephson junctions, three loops, and a superconducting transmission line.…
Embedded neural-network inference can leak information through timing side channels, including leakage caused by the evaluation of activation functions. This work proposes a constant-time implementation methodology for activation functions…