Related papers: A Low-Power 20-Gb/s Discrete-Time Analog Front-End…

We present a power efficient clock-less fully asynchronous bit-serial Low Voltage Differential Signaling (LVDS) link with event-driven instant wake-up and self-sleep features, optimized for high speed inter-chip communication of…

Analog-to-digital conversion (ADC) is a key bottleneck in scaling DSP-centric receiver architectures to multiGigabit/s speeds. Recent information-theoretic results, obtained under ideal channel conditions (perfect synchronization, no…

High resolution analog to digital converters (ADCs) are conventionally used at the receiver terminals to store an accurate digital representation of the received signal, thereby allowing for reliable decoding of transmitted messages.…

Time-domain ADCs are attractive for high-speed wireline receivers, as time resolution scales favorably with advanced CMOS technologies, enabling multi-GS/s single-channel sampling rates. However, conventional time-domain ADCs require…

In this paper, we propose an analog network coding scheme with differential modulation (ANC-DM) using amplify-and-forward protocol for bidirectional relay networks when neither the source nodes nor the relay knows the channel state…

We present the design, fabrication, and measurement of a monolithically integrated optical receiver analog front end, where low power operation is a primary consideration with a goal of supporting 56 Gbaud intensity modulated direct detect…

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB.…

In task-based quantization, a multivariate analog signal is transformed into a digital signal using a limited number of low-resolution analog-to-digital converters (ADCs). This process aims to minimize a fidelity criterion, which is…

This work presents a fully discrete, low cost digital isolator requiring no specialized ICs and implemented entirely with general purpose transistors and a two layer PCB embedded air core transformer. The design avoids vendor lock in and…

This paper proposes a novel foreground linearization scheme for a high-speed CS-DAC. The technique leverages neural networks (NNs) to derive a LUT that maps the inverse of the DAC transfer characteristic onto the input codes. The algorithm…

This paper introduces a backpropagation-based technique for the calibration of the mismatch errors of time-interleaved analog to digital converters (TI-ADCs). This technique is applicable to digital receivers such as those used in coherent…

High sampling speed can be achieved using multiple Analog-to-Digital Converters (ADCs) based on the Time-Interleaving A/D Conversion (TIADC) technique. Various types of methods were proposed to correct the mismatch errors among parallel ADC…

The task of this work was to design and later produce a low-power (single supply 5 - 30 V, dual supply +-2.5 V and +-15 V) rail-to-rail operational amplifier aRD820 with low voltage noise (<4 uV, p-p. 0.1 to 10 Hz), ultralow input bias…

Novel analog-to-digital converter (ADC) architectures are motivated by the demand for rising sampling rates and effective number of bits (ENOB). The main limitation on ENOB in purely electrical ADCs lies in the relatively high jitter of…

The design of a high-precision time-to-digital converter (TDC) based on a multiphase clock implemented using a single field-programmable gate array is discussed in this paper. The TDC can increase the resolution of the measurement by using…

A switched-capacitor matrix multiplier is presented for approximate computing and machine learning applications. The multiply-and-accumulate operations perform discrete-time charge-domain signal processing using passive switches and 300 aF…

Laser synchronization is a technique that locks the wavelength of a free-running laser to that of the reference laser, thereby enabling synchronous changes in the wavelengths of the two lasers. This technique is of crucial importance in…

Asynchronous and cyclostationary impulsive noise can severely impact the bit-error-rate (BER) of OFDM-based powerline communication systems. In this paper, we analyze an adaptive nonlinear analog front end filter that mitigates various…

This paper presents the design and analysis of a wearable CMOS biosensor with three different designs of energy-resolution scalable time-based resistance to digital converters (RDC), targeted towards either minimizing the energy/conversion…

Based on an equivalent model for quantizers with noisy inputs recently presented in [35], we propose a method of digital dithering at the transmitter that may significantly reduce the resolution requirements of MIMO downlink Digital to…