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Related papers: LBICA: A Load Balancer for I/O Cache Architectures

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Checkpointing large amounts of related data concurrently to stable storage is a common I/O pattern of many HPC applications. However, such a pattern frequently leads to I/O bottlenecks that lead to poor scalability and performance. As…

Distributed, Parallel, and Cluster Computing · Computer Science 2021-03-04 Bogdan Nicolae , Adam Moody , Gregory Kosinovsky , Kathryn Mohror , Franck Cappello

Load balancing at transport layer is an important function in data centers, content delivery networks, and mobile networks, where per-connection consistency (PCC) has to be met for optimal performance. Cloud-native L4 load balancers are…

Networking and Internet Architecture · Computer Science 2020-03-27 Ashkan Aghdai , Michael I. -C. Wang , Yang Xu , Charles H. -P. Wen , H. Jonathan Chao

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are used for running various server applications. Depending on the application that is run on the system, remote memory…

Distributed, Parallel, and Cluster Computing · Computer Science 2019-08-13 Murthy Durbhakula

Although the decentralized storage technology based on the blockchain can effectively realize secure data storage on cloud services. However, there are still some problems in the existing schemes, such as low storage capacity and low…

Cryptography and Security · Computer Science 2024-04-03 Zijian Zhou , Caimei Wang , Xiaoheng Deng , Jianhao Lu , Qilue Wen , Chen Zhang , Hong Li

Distributed systems store data objects redundantly to balance the data access load over multiple nodes. Load balancing performance depends mainly on 1) the level of storage redundancy and 2) the assignment of data objects to storage nodes.…

Distributed, Parallel, and Cluster Computing · Computer Science 2023-12-19 Mehmet Aktas , Emina Soljanin

Flash memories intended for SSD and mobile applications need to provide high random I/O performance. This requires using efficient schemes for reading small chunks of data (e.g. 0.5KB - 4KB) from random addresses. Furthermore, in order to…

Information Theory · Computer Science 2012-03-01 Eran Sharon , Idan Alrod

Enterprise SSDs integrate numerous computing resources (e.g., ARM processor and onboard DRAM) to satisfy the ever-increasing performance requirements of I/O bursts. While these resources substantially elevate the monetary costs of SSDs, the…

Operating Systems · Computer Science 2025-09-15 Shushu Yi , Yuda An , Li Peng , Xiurui Pan , Qiao Li , Jieming Yin , Guangyan Zhang , Wenfei Wu , Diyu Zhou , Zhenlin Wang , Xiaolin Wang , Yingwei Luo , Ke Zhou , Jie Zhang

The rapid development of multi-core system and increase of data-intensive application in recent years call for larger main memory. Traditional DRAM memory can increase its capacity by reducing the feature size of storage cell. Now further…

Hardware Architecture · Computer Science 2016-06-13 Shenchen Ruan , Haixia Wang , Dongsheng Wang

Heterogeneity is becoming increasingly ubiquitous in modern large-scale computer systems. Developing good load balancing policies for systems whose resources have varying speeds is crucial in achieving low response times. Indeed, how best…

Performance · Computer Science 2020-06-26 Kristen Gardner , Jazeem Abdul Jaleel , Alexander Wickeham , Sherwin Doroudi

Modern cloud servers routinely co-locate multiple latency-sensitive microservice instances to improve resource efficiency. However, the diversity of microservice behaviors, coupled with mutual performance interference under simultaneous…

Distributed, Parallel, and Cluster Computing · Computer Science 2026-03-02 Dingyu Yang , Fanyong Kong , Jie Dai , Shiyou Qian , Shuangwei Li , Jian Cao , Guangtao Xue , Gang Chen

Zoned Namespace SSDs (ZNS) are introduced recently to mitigate the block interface penalties of flash-based SSDs. It is a good opportunity for flash cache to address cache throughput and write amplification (WA) issues by fully controlling…

Performance · Computer Science 2024-10-16 Chongzhuo Yang , Chang Guo , Ming Zhao , Zhichao Cao

Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a general-purpose host processor with a many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring a…

Hardware Architecture · Computer Science 2018-08-30 Andreas Kurth , Pirmin Vogel , Andrea Marongiu , Luca Benini

High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is…

Hardware Architecture · Computer Science 2021-03-30 Majid Jalili , Mattan Erez

Serverless computing is an emerging cloud computing paradigm that can reduce costs for cloud providers and their customers. However, serverless cloud platforms have stringent performance requirements (due to the need to execute short…

Distributed, Parallel, and Cluster Computing · Computer Science 2024-09-04 S. Qi , H. Moore , N. Hogade , D. Milojicic , C. Bash , S. Pasricha

The development of high-speed storage devices such as NVMe SSDs has shifted the primary I/O bottleneck from hardware to software. Modern database systems also rely on kernel-based I/O paths, where frequent system call invocations and…

Databases · Computer Science 2026-03-06 Hongsu Byun , Seungjae Lee , Honghyeon Yoo , Myoungjoon Kim , Sungyong Park

Modern SoCs integrate multiple CPU cores and Hardware Accelerators (HWAs) that share the same main memory system, causing interference among memory requests from different agents. The result of this interference, if not controlled well, is…

Hardware Architecture · Computer Science 2015-05-29 Hiroyuki Usui , Lavanya Subramanian , Kevin Chang , Onur Mutlu

Optimal page replacement is an important problem in efficient buffer management. The range of replacement strategies known in the literature varies from simple but efficient FIFO-based algorithms to more accurate but potentially costly…

We study the problem of optimizing data storage and access costs on the cloud while ensuring that the desired performance or latency is unaffected. We first propose an optimizer that optimizes the data placement tier (on the cloud) and the…

Skiplists are widely used for in-memory indexing in many key-value stores, such as RocksDB and LevelDB, due to their ease of implementation and simple concurrency control mechanisms. However, traditional skiplists suffer from poor cache…

Distributed, Parallel, and Cluster Computing · Computer Science 2025-09-18 Yicong Luo , Senhe Hao , Brian Wheatman , Prashant Pandey , Helen Xu

Modern commercial-off-the-shelf (COTS) multicore processors have advanced memory hierarchies that enhance memory-level parallelism (MLP), which is crucial for high performance. To support high MLP, shared last-level caches (LLCs) are…

Hardware Architecture · Computer Science 2025-07-23 Connor Sullivan , Alex Manley , Mohammad Alian , Heechul Yun